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參數(shù)資料
| 型號： | 934056904126 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 小信號晶體管 |
| 英文描述： | 1000 mA, 40 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92 |
| 封裝： | PLASTIC, SPT, SC-43, 3 PIN |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 60K |
| 代理商： | 934056904126 |
December 1990
8
Philips Semiconductors
Product specication
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: LSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max.
min. max.
min.
max.
tPHL/ tPLH
propagation delay
MR to DIR, DOR
69
25
20
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
SI to DIR
77
28
22
235
47
40
295
59
50
355
71
60
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
SO to DOR
102
37
30
315
63
54
395
79
67
475
95
81
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
DOR to Qn
11
4
3
35
7
6
45
9
8
55
11
9
ns
2.0
4.5
6.0
Fig.10
tPHL/ tPLH
propagation delay
SO to Qn
113
41
33
345
69
59
430
86
73
520
104
88
ns
2.0
4.5
6.0
Fig.14
tPLH
propagation delay/
ripple through delay
SI to DOR
2.5
0.9
0.7
8.0
1.6
1.3
10
2.0
1.6
12
2.4
1.9
s
2.0
4.5
6.0
Fig.10
tPLH
propagation delay/
bubble-up delay
SO to DIR
3.3
1.2
1.0
10.0
2.0
1.6
12
2.5
2.0
15
3.0
2.4
s
2.0
4.5
6.0
Fig.7
tPZH/ tPZL
3-state output enable
OE to Qn
52
19
15
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.16
tPHZ/ tPLZ
3-state output disable
OE to Qn
50
18
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.16
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.14
tW
SI pulse width
HIGH or LOW
50
10
9
14
5
4
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.6
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