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參數(shù)資料
| 型號(hào)： | 933999380112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 64 X 4 OTHER FIFO, 108 ns, PDIP16 |
| 封裝： | PLASTIC, SOT-38Z, DIP-16 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 933999380112 |
September 1993
4
Philips Semiconductors
Product specication
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Fig.4 Functional diagram.
MGA679
DIR
OE
SI
MR
DnA
4
DIR
SI
DOR
SO
DATA INPUT
A
4
SO A
DOR A
QnA
7403
FIFO A
DIR
OE
SI
MR
DnB
B
4
SOB
DOR B
Q nB
7403
FIFO B
DATA OUTPUT
OE
MR
FUNCTIONAL DESCRIPTION
A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D0 to D3 is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q0 to Q3).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
Expanded format (see Fig.17)
The DOR and DIR signals are used to
allow the “7403” to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is only possible with
typical devices.
Parallel expansion
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
Serial expansion
Serial expansion is accomplished by:
tying the data outputs of the first
device to the data inputs of the
second device
connecting the DOR pin of the first
device to the SI pin of the second
device
connecting the SO pin of the first
device to the DIR pin of the second
device.
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