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參數(shù)資料
| 型號(hào)： | 933995410602 |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 接收器 |
| 英文描述： | FM, AUDIO DEMODULATOR, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, SOT-109-1, MS-012AC, SO-16 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | 933995410602 |
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Philips Semiconductors
Product specification
SA614A
Low power FM IF system
1997 Nov 07
7
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NE604A TEST CIRCUIT
SA604A
MUTE
AUDIO
RSSI
DATA
8765
4
3
2
1
SA602
+6V
100nF
10nF
47pF
22pF
100nF
5.6pF
44.545
3rd OVERTURE
XTAL
SFG455A3
OUT
C–MSG
FILTER
455kHz
Q=20
SFG455A3
+6V
4V
10pF
3V
2V
1V
–0
–20
–40
–60
–80
10
100
1k
10k
100k
–120
–100
–80
–60
–40
–20
AUDIO
OUT
–
‘C’
MESSAGE
WEIGHTED
614A IF INPUT (
V) (1500)
(0dB
REF
=
RECOVERED
AUDIO
FOR
+8kHz
PEAK
DEVIA
TION
(dB)
–
AUDIO
RSSI (VOLTS)
THD + NOISE
AM (80% MOD)
NOISE
602 RF INPUT (dBm) (50
)
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
22pF
1nF
0.5
to
1.3
H
5.5
H
6.8
F
0.21
to
0.28
H
100k
0.1
F
SR00327
Figure 5. Typical Application Cellular Radio (45MHz to 455kHz)
CIRCUIT DESCRIPTION
The SA614A is a very high gain, high frequency device. Correct
operation is not possible if good RF layout and gain stage practices
are not used. The SA614A cannot be evaluated independent of
circuit, components, and board layout. A physical layout which
correlates to the electrical limits is shown in Figure 3. This
configuration can be used as the basis for production layout.
The SA614A is an IF signal processing system suitable for IF
frequencies as high as 21.4MHz. The device consists of two limiting
amplifiers, quadrature detector, direct audio output, muted audio
output, and signal strength indicator (with log output characteristic).
The sub-systems are shown in Figure 4. A typical application with
45MHz input and 455kHz IF is shown in Figure 5.
IF Amplifiers
The IF amplifier section consists of two log-limiting stages. The first
consists of two differential amplifiers with 39dB of gain and a small
signal bandwidth of 41MHz (when driven from a 50
source). The
output of the first limiter is a low impedance emitter follower with
1k
of equivalent series resistance. The second limiting stage
consists of three differential amplifiers with a gain of 62dB and a
small signal AC bandwidth of 28MHz. The outputs of the final
differential stage are buffered to the internal quadrature detector.
One of the outputs is available at Pin 9 to drive an external
quadrature capacitor and L/C quadrature tank.
Both of the limiting amplifier stages are DC biased using feedback.
The buffered output of the final differential amplifier is fed back to the
input through 42k
resistors. As shown in Figure 4, the input
impedance is established for each stage by tapping one of the
feedback resistors 1.6k
from the input. This requires one
additional decoupling capacitor from the tap point to ground.
42k
15
16
1
1.6k
40k
V+
70014
7k
SR00328
Figure 6. First Limiter Bias
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