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參數(shù)資料
| 型號(hào)： | 933975610623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬波形發(fā)生器 |
| 英文描述： | PULSE, 0.5 MHz, TIMER, PDSO8 |
| 封裝： | PLASTIC, SOT-96, SO-8 |
| 文件頁(yè)數(shù)： | 9/9頁(yè) |
| 文件大小： | 66K |
| 代理商： | 933975610623 |
Philips Semiconductors Linear Products
Product specification
ICM7555
General purpose CMOS timer
August 31, 1994
345
Astable Operation
If the circuit is connected as shown in Figure 2, it will trigger itself
and free run as a multivibrator. The external capacitor charges
through RA and RB and discharges through RB only. Thus, the duty
cycle (D) may be precisely set by the ratio of these two resistors. In
this mode of operation, the capacitor charges and discharges
between 1/3 VDD and 2/3 VDD. Since the charge rate and the
threshold levels are directly proportional to the supply voltage, the
frequency of oscillation is independent of the supply voltage.
1.38
(RA + 2RB)
RA + 2RB
F =
C
D =
RA + RB
Monostable Operation
In this mode of operation, the timer functions as a one-shot. Initially,
the external capacitor (C) is held discharged by a transistor inside
the timer. Upon application of a negative pulse to Pin 2,TRIGGER,
the internal flip-flop is set which releases the low impedance on
DISCHARGE; the external capacitor charges and drives the
OUTPUT High. The voltage across the capacitor increases
exponentially with a time constant t = RAC. When the voltage
across the capacitor equals 2/3 V+, the comparator resets the
flip-flop, which in turn discharges the capacitor rapidly and also
drives the OUTPUT to its low state. TRIGGER must return to a high
state before the OUTPUT can return to a low state.
Control Voltage
The CONTROL VOLTAGE terminal permits the two trip voltages for
the THRESHOLD and TRIGGER internal comparators to be
controlled. This provides the possibility of oscillation frequency
modulation in the astable mode, or even inhibition of oscillation,
depending on the applied voltage. In the monostable mode, delay
times can be changed by varying the applied voltage to the
CONTROL VOLTAGE pin.
RESET
The RESET terminal is designed to have essentially the same trip
voltage as the standard bipolar 555, i.e., 0.6 to 0.7V. At all supply
voltages it represents an extremely high input impedance. The
mode of operation of the RESET function is, however, much
improved over the standard bipolar 555 in that it controls only the
internal flip-flop, which in turn controls simultaneously the state of
the OUTPUT and DISCHARGE pins. This avoids the multiple
threshold problems sometimes encountered with slow falling edges
in the bipolar devices.
1
2
3
4
8
7
6
5
GND
TRIGGER
OUTPUT
RESET
DISHCARGE
THRESHOLD
CONTROL
VOLTAGE
OUTPUT
V
DD
R
A
B
R
V
DD
V
DD
C
Figure 2. Astable Operation
1
2
3
4
8
7
6
5
TRIGGER
OUTPUT
RESET
DISHCARGE
THRESHOLD
CONTROL
VOLTAGE
V
DD
C
OPTIONAL
CAPACITOR
VDD < 18V
t = 1.05 RA C
R
A
Figure 3. Monostable Operation
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