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參數(shù)資料
| 型號： | 933714740653 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 封裝： | 3.90 MM, PLASITC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 933714740653 |
8
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU.
Figure 4-2.
AVR CPU General Purpose Working Registers
Note:
A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement
only 16 registers. For reasons of compatibility the registers are numbered R16...R31, not R0...R15.
Most of the instructions operating on the Register File have direct access to all registers, and most of them are sin-
gle cycle instructions.
4.4.1
The X-register, Y-register, and Z-register
Registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are
defined as described in Figure 4-3.
Figure 4-3.
The X-, Y-, and Z-registers
70
R16
R17
General
R18
Purpose
…
Working
R26
X-register Low Byte
Registers
R27
X-register High Byte
R28
Y-register Low Byte
R29
Y-register High Byte
R30
Z-register Low Byte
R31
Z-register High Byte
15
XH
XL
0
X-register
70
7
0
R27
R26
15
YH
YL
0
Y-register
70
7
0
R29
R28
15
ZH
ZL
0
Z-register
70
7
0
R31
R30
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