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參數(shù)資料
| 型號： | 933713380653 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 933713380653 |
1998 Feb 23
6
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset;
positive-edge trigger
74HC/HCT74
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Note to HCT types
The value of additional quiescent supply current (
I
CC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
nD
0.70
nRD
0.70
nSD
0.80
nCP
0.80
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
nCP to nQ, nQ
18
35
44
53
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
nSD to nQ, nQ
23
40
50
60
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
nRD to nQ, nQ
24
40
50
60
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
18
9
23
27
ns
4.5
Fig.6
tW
set or reset pulse width
LOW
16
9
20
24
ns
4.5
Fig.7
trem
removal time
set or reset
6
1
8
9
ns
4.5
Fig.7
tsu
set-up time
nD to nCP
12
5
15
18
ns
4.5
Fig.6
th
hold time
nCP to nD
3
ns
4.5
Fig.6
fmax
maximum clock pulse
frequency
27
54
22
18
MHz
4.5
Fig.6
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