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參數(shù)資料
| 型號(hào)： | 933670570652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20 |
| 封裝： | SOT-146-1, DIP-20 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 79K |
| 代理商： | 933670570652 |
December 1990
9
Philips Semiconductors
Product specication
8-bit universal shift register; 3-state
74HC/HCT299
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Q0, Q7
22
37
46
56
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
CP to I/On
22
37
46
56
ns
4.5
Fig.6
tPHL
propagation delay
MR to Q0, Q7 or I/On
27
46
58
69
ns
4.5
Fig.7
tPZH/ tPZL
3-state output enable time
OEn to I/On
19
30
38
45
ns
4.5
Fig.9
tPHZ
3-state output disable time
OEn to I/On
24
37
46
56
ns
4.5
Fig.9
tPLZ
3-state output disable time
OEn to I/On
20
32
40
48
ns
4.5
Fig.9
tTHL/ tTLH
output transition time
bus driver (I/On)
5
12
15
18
ns
4.5
Fig.6
tTHL/ tTLH
output transition time
standard (Q0, Q7)
7
15
19
22
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
20
10
25
30
ns
4.5
Fig.6
tW
master reset pulse width
LOW
20
11
25
30
ns
4.5
Fig.7
trem
removal time
MR to CP
10
2
9
11
ns
4.5
Fig.7
tsu
set-up time
I/On, DSR, DSL to CP
25
14
31
38
ns
4.5
Fig.6
tsu
set-up time
S0, S1 to CP
32
18
40
48
ns
4.5
Fig.8
th
hold time
I/On, DSR, DSL to CP
0
11
0
ns
4.5
Fig.6
th
hold time
S0, S1 to CP
0
17
0
ns
4.5
Fig.8
fmax
maximum clock pulse
frequency
25
42
20
17
MHz
4.5
Fig.6
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