參數(shù)資料
型號(hào)： 89HPES22H16ZABR
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA484
封裝： 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FCBGA-484
文件頁(yè)數(shù)： 8/36頁(yè)
文件大?。?/td> 784K
代理商： 89HPES22H16ZABR
16 of 36
November 17, 2008
IDT 89HPES22H16 Data Sheet
Figure 5 GPIO AC Timing Waveform
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol Reference
Edge
Min Max Unit
Timing
Diagram
Reference
GPIO
GPIO[31:0]1
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
are asynchronous.
Tpw_13b2
2. The values for this symbol were determined by calculation, not by testing.
None
50
—
ns
Table 11 GPIO AC Timing Characteristics
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Referenc
e
JTAG
JTAG_TCK
Tper_16a
none
50.0
—
ns
Thigh_16a,
Tlow_16a
10.0
25.0
ns
JTAG_TMS1,
JTAG_TDI
1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b
JTAG_TCK rising
2.4
—
ns
Thld_16b
1.0
—
ns
JTAG_TDO
Tdo_16c
JTAG_TCK falling
—
20
ns
Tdz_16c2
2. The values for this symbol were determined by calculation, not by testing.
—20
ns
JTAG_TRST_N
Tpw_16d2
none
25.0
—
ns
Table 12 JTAG AC Timing Characteristics
Tpw_13b
EXTCLK
GPIO (asynchronous input)
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