參數(shù)資料
型號： 8761CYILFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： XO, clock
英文描述： 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù)： 3/16頁
文件大小： 284K
代理商： 8761CYILFT
8761CYI
www.idt.com
REV. C JULY 27, 2010
11
ICS8761I
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8761I. In this
example, the input is driven by an 18pF parallel crystal. The
decoupling capacitors should be physically located near the
power pin. For ICS8761I, the unused clock outputs can be left
floating. The optional C1 and C2 are spare footprints for frequency
fine tuning.
FIGURE 3. ICS8761I CLOCK GENERATOR SCHEMATIC EXAMPLE
(U1,44)
C9
0.1u
(U1,62)
C14
0.1u
C11
0.1u
C16
10u
Receiv er
Zo = 50
(U1,58)
R5
1K
VDDO=3.3V
(U1,46)
C7
0.1u
(U1,54)
VDD
SP = Spare, Not Install
VDD
C10
0.1u
C6
0.1u
VDD=3.3V
R3
36
VDD
Receiv er
Set Logic
Input to '1'
RD2
1K
(U1,9)
R1
36
Receiv er
Zo = 50
R4
36
To Logic
Input pins
C12
0.1u
X1
25MHz,18pF
C4
0.1u
R2
36
RU1
1K
VDDO
C2
SP
Zo = 50
C17
0.1u
R6
1K
(U1,19)
U1
ICS8761
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19
20 21 22
23 24 25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52 51
50 49
48
47
46
45
44
43
42
41
40
63 62
61 60 59
58 57 56
55 54
53
64
REF_CLK
GND
XTAL1
XTAL2
VDD
XTAL_SEL
PLL_SEL
VDDA
VDD
D_SELC0
D_SELC1
OEC
OEA
D_SELA0
D_SELA1
GND
GN
D
QA0 VD
D
O
A
QA1
GN
D
QA2 VD
D
O
A
QA3 GN
D
QB0
D_SELD0
D_SELD1
OED
OEB
D_SELB0
D_SELB1
GND
QB3
VD
D
O
B
QB2
GN
D
QB1
VD
D
O
B
GN
D
QD
2
VD
D
O
D
QD
3
GND
FB_OUT
VDDOFB
FB_IN
VDD
FBDIV_SEL0
FBDIV_SEL1
MR
VDD
QC
0
VD
D
O
C
QC
1
GN
D
QC
2
VD
D
O
C
QC
3
GN
D
QD
0
VD
D
O
D
QD
1
GN
D
Set Logic
Input to '0'
VDDO
C8
0.1u
VDD
(U1,40)
C15
0.1u
To Logic
Input pins
C5
0.1u
(U1,23)
C3
0.1u
VDDO
RU2
SP
VDD
Logic Input Pin Examples
(U1,27)
(U1,31)
VDD
FB
C13
0.1u
C1
SP
(U1,5)
Receiv er
RD1
SP
VDDO
Zo = 50
(U1,50)
ICS8761I
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