參數(shù)資料
型號(hào)： 8406601XA
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： CMOS Programmable Peripheral Interface
中文描述： 24 I/O, PIA-GENERAL PURPOSE, CQCC44
封裝： CERAMIC, LCC-44
文件頁數(shù)： 26/26頁
文件大?。?/td> 234K
代理商： 8406601XA
26
82C55A
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j
x 45
o
D3
B
h x 45
o
A
A1
E
L
L3
e
B3
L1
D2
D1
e
1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010
E H
S
S
0.010
E F
S
S
-E-
0.007
E F
M
S H S
B1
-H-
-F-
J44.A
MIL-STD-1835 CQCC1-N44 (C-5)
44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.064
0.120
1.63
3.05
6, 7
A1
0.054
0.088
1.37
2.24
-
B
0.033
0.039
0.84
0.99
4
B1
0.022
0.028
0.56
0.71
2, 4
B2
0.072 REF
1.83 REF
-
B3
0.006
0.022
0.15
0.56
-
D
0.640
0.662
16.26
16.81
-
D1
0.500 BSC
12.70 BSC
-
D2
0.250 BSC
6.35 BSC
-
D3
-
0.662
-
16.81
2
E
0.640
0.662
16.26
16.81
-
E1
0.500 BSC
12.70 BSC
-
E2
0.250 BSC
6.35 BSC
-
E3
-
0.662
-
16.81
2
e
0.050 BSC
1.27 BSC
-
e1
0.015
-
0.38
-
2
h
0.040 REF
1.02 REF
5
j
0.020 REF
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.90
2.41
-
L3
0.003
0.015
0.08
0.38
-
ND
11
11
3
NE
11
11
3
N
44
44
3
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
相關(guān)PDF資料
PDF描述
8406602QA MB 61C 61#20 SKT RECP
8406601QA CMOS Programmable Peripheral Interface
8408 Quad 8-Bit Multiplying CMOS D/A Converter with Memory
8408RPFB Quad 8-Bit Multiplying CMOS D/A Converter with Memory
8408RPFE Quad 8-Bit Multiplying CMOS D/A Converter with Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
8406601XX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral Interface
8406602QA 制造商:Intersil Corporation 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTRFC 8CDIP - Rail/Tube
8406602QX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral Interface
8406602XA 制造商:Intersil Corporation 功能描述:CMOS PROGRAMMABLE PERIPHERAL INTRFC 44CLCC - Rail/Tube
8406602XX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral Interface
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*