
Intel
82801BA ICH2 Datasheet
9-65
LPC Interface Bridge Registers (D31:F0)
5
AC97 Status (AC97_STS)
—R/WC.
The value of this bit will be maintained through a G3 state and
is not affected by a hard reset caused by a CF9h write.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit gets
set only from the following two cases:
1. ACSDIN[1] or ACSDIN[0] is high and BITCLK is not oscillating, or
2. The GSCI bit is set (section 13.2.9, NAMBAR +30h, bit 0)
4
USB Controller 2 Status (USB2_STS)
—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB Controller 2 needs to cause a wake. Wake event will be generated
if the corresponding USB2_EN bit is set.
3
USB Controller 1 Status (USB1_STS)
—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB Controller 1 needs to cause a wake. Wake event will be generated
if the corresponding USB1_EN bit is set.
2
Reserved.
1
Thermal Interrupt Override Status (THRMOR_STS)
—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = This bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling the
processor’s clock at the THRM_DTY ratio. This will not cause an SMI#, SCI, or wake event.
0
Thermal Interrupt Status (THRM_STS)
—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL bit.
Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also generate
a power management event (SCI or SMI#).
Bit
Description
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