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參數(shù)資料
| 型號(hào)： | 7P512FLG0602I15 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 256K X 16 FLASH 12V PROM CARD, 150 ns, XMA68 |
| 封裝： | CARD-68 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 344K |
| 代理商： | 7P512FLG0602I15 |
PCMCIA Flash Memory Card
FLG Series
3
White Electronic Designs
June, 2003
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
Pin
Signal name
I/O
Function
Active
1
GND
Ground
2
DQ3
I/O
Data bit 3
3
DQ4
I/O
Data bit 4
4
DQ5
I/O
Data bit 5
5
DQ6
I/O
Data bit 6
6
DQ7
I/O
Data bit 7
7
CE1#
I
Card enable 1
LOW
8
A10
I
Address bit 10
9
OE#
I
Output enable
LOW
10
A11
I
Address bit 11
11
A9
I
Address bit 9
12
A8
I
Address bit 8
13
A13
I
Address bit 13
14
A14
I
Address bit 14
15
WE#
I
Write Enable
LOW
16
RDY/BSY#
O
Ready/Busy
N.C.
17
VCC
Supply Voltage
18
VPP1
Prog. Voltage
19
A16
I
Address bit 16
20
A15
I
Address bit 15
21
A12
I
Address bit 12
22
A7
I
Address bit 7
23
A6
I
Address bit 6
24
A5
I
Address bit 5
25
A4
I
Address bit 4
26
A3
I
Address bit 3
27
A2
I
Address bit 2
28
A1
I
Address bit 1
29
A0
I
Address bit 0
30
DQ0
I/O
Data bit 0
31
DQ1
I/O
Data bit 1
32
DQ2
I/O
Data bit 2
33
WP
O
Write Potect
HIGH
34
GND
Ground
Pin
Signal name
I/O
Function
Active
35
GND
Ground
36
CD1#
O
Card Detect 1
LOW
37
DQ11
I/O
Data bit 11
38
DQ12
I/O
Data bit 12
39
DQ13
I/O
Data bit 13
40
DQ14
I/O
Data bit 14
41
DQ15
I
Data bit 15
42
CE2#
I
Card Enable 2
LOW
43
VS1
O
Voltage Sense 1
N.C.
44
RFU
Reserved
45
RFU
Reserved
46
A17
I
Address bit 17
256KB(2)
47
A18
I
Address bit 18
512KB(2)
48
A19
I
Address bit 19
1MB(2)
49
A20
I
Address bit 20
2MB(2)
50
A21
I
Address bit 21
4MB(2,3)
51
VCC
Supply Voltage
52
VPP2
Prog. Voltage
53
A22
I
Address bit 22
8MB(2,3)
54
A23
I
Address bit 23
N.C.
55
A24
I
Address bit 24
N.C.
56
A25
I
Address bit 25
N.C.
57
VS2
O
Voltage Sense 2
N.C.
58
RST
I
Card Reset
N.C.
59
Wait#
O
Extended Bus cycle
LOW(1)
60
RFU
Reserved
61
REG#
I
Attrib Mem Select
62
BVD2
O
Bat. Volt. Detect 2
(1)
63
BVD1
O
Bat. Volt. Detect 1
(1)
64
DQ8
I/O
Data bit 8
65
DQ9
I/O
Data bit 9
66
DQ10
O
Data bit 10
67
CD2#
O
Card Detect 2
LOW
68
GND
Ground
PINOUT
Notes:
1.
WAIT#, BVD1 and BVD2 are driven high for compatibility
2.
Shows density for which specied address bit is MSB. Higher order address bits are no connects (i.e. 4MB A21 is MSB A22 - A25 are NC).
3.
For the 3MB card the memory will wrap at the 4MB boundary, for the 5MB card the memory will wrap at the 8MB boundary.
54.0mm 0.10
(2.126”)
10.0mm MIN
(0.400”)
1.6mm 0.05
(0.063”)
1.0mm 0.05
(0.039”)
1.0mm 0.05
(0.039”)
3.3mm T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
Interconnect area
10.0mm MIN
(0.400”)
3.0mm MIN
85.6mm 0.20
(3.370”)
Substrate area
MECHANICAL
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