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參數(shù)資料
| 型號： | 79RC32H435-350BC |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數(shù)： | 9/53頁 |
| 文件大?。?/td> | 444K |
| 代理商： | 79RC32H435-350BC |
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9 of 53
January 19, 2006
IDT 79RC32435
EJTAG_TMS
I
EJTAG Mode
. The value on this signal controls the test mode select of the
EJTAG Controller. When using the JTAG boundary scan, this pin should be left
disconnected (since there is an internal pull-up) or driven high.
JTAG_TRST_N
I
JTAG Reset
. This active low signal asynchronously resets the boundary scan
logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external
pull-up on the board is recommended to meet the JTAG specification in cases
where the tester can access this signal. However, for systems running in func-
tional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high.
JTAG_TCK
I
JTAG Clock
. This is an input test clock used to clock the shifting of data into or
out of the boundary scan logic, JTAG Controller, or the EJTAG Controller.
JTAG_TCK is independent of the systemand the processor clock with a nom-
nal 50% duty cycle.
JTAG_TDO
O
JTAG Data Output
. This is the serial data shifted out fromthe boundary scan
logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted
out, this signal is tri-stated.
JTAG_TDI
I
JTAG Data Input
. This is the serial data input to the boundary scan logic, JTAG
Controller, or the EJTAG Controller.
System
CLK
I
Master Clock.
This is the master clock input. The processor frequency is a mul-
tiple of this clock frequency. This clock is used as the systemclock for all mem-
ory and peripheral bus operations.
EXTBCV
I
Load External Boot Configuration Vector.
When this pin is asserted (i.e.,
high) the boot configuration vector is loaded froman externally supplied value
during a cold reset. When this pin is negated, the boot configuration vector is
taken fromthe NVRAMlocated on-chip.
EXTCLK
O
External Clock.
This clock is used for all memory and peripheral bus opera-
tions.
COLDRSTN
I
Cold Reset.
The assertion of this signal initiates a cold reset. This causes the
processor state to be initialized, boot configuration to be loaded, and the internal
PLL to lock onto the master clock (CLK).
RSTN
I/O
Reset.
The assertion of this bidirectional signal initiates a warmreset. This sig-
nal is asserted by the RC32435 during a warmreset.
S ignal
Type
Name/Desc ription
Table 1 Pin Description (Part 6 of 6)
相關PDF資料 |
PDF描述 |
|---|---|
| 79RC32H435-350BCI | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32H435-400BC | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32H435-400BCI | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32438 | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32K438-200BB | IDTTM InterpriseTM Integrated Communications Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 79RC32H435-350BCG | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| 79RC32H435-350BCGI | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| 79RC32H435-350BCI | 制造商:Integrated Device Technology Inc 功能描述:MPU RC32435 RISC 32-Bit 350MHz 2.5V/3.3V 256-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:COMMUNICATIONS PROCESSOR 256CABGA - Bulk |
| 79RC32H435-400BC | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| 79RC32H435-400BCG | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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