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| 型號： | 78Q8430STEM#DB |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 21/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD 78Q8430 |
| 標準包裝： | 1 |
| 系列： | * |
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78Q8430 Data Sheet
DS_8430_001
28
Rev. 1.2
6.3.2.1
Using the Setup Transmit Data Register
The Setup Transmit Data Register (STDR) can be used to control the way in which 32-bit data words are
transferred to the transmit FIFO. The STDR can be changed on a word-by-word basis to change the
network endianness or buffer-byte-alignment, or the STDR can be used to setup the transfer of an entire
buffer of transmit data. A new frame must be initialized by a write to the PCWR before the STDR is setup
for transferring frame data to the QUE.
The Count field of the STDR contains one less than the number of writes to the TDR that will be needed
to complete the transfer of the buffer. The Start Offset field contains the number of bytes in the first write
to the TDR to ignore. The End Offset field contains the number of bytes in the last write (when the Count
field is equal to zero) to ignore.
Table 22: Transmit Data Buffer Example
32-bit Write Data
Transmit Order:
Byte-1
Byte-2
Byte-3
Byte-4
Start Offset = 2
X
B1
B2
B3
B4
B5
B6
Count decrements for
each write
…
B
N-4
B
N-3
B
N-2
N-1
End Offset = 3
B
X
N
X
Notes:
1.
The End Offset will continue to be applied as long as the COUNT field of the STDR contains zero. If
a non-zero End Offset is used, it must be cleared at the end of the block transfer.
2.
The COUNT field must expire before the PSZR expires. Frames that are entirely contained within
The Endian field of the STDR is used to set the transmit order of the data written on the bus, or how host
bus write data bytes are mapped to transmit buffer bytes. If the Endian bit is set then the most significant
byte of the host bus as defined by the logical endianness, is mapped to the first transmitted byte in the
buffer, otherwise, the least significant byte is mapped to the first transmitted byte.
6.3.2.2
Preloading Transmit Data
A transmit QUE signals the MAC transmitter that it is ready to transmit by asserting the QUE Data Ready
bit (QDR) in its QUE Status Register (QSR). The default behavior of the QDR for a transmit QUE is to
assert anytime the QUE contains any data. This means that a transmit QUE can potentially begin
transmitting as soon as the first BLOCK is added to the QUE. Once the QUE begins transmitting, data for
the packet being transmitted must be added to the QUE faster than the transmitter removes it or a TX
FIFO under-run condition will eventually abort the packet (see TPSR).
In the event that interrupt latency, host bus performance, or other issues may prevent the host from
loading data into the QUE faster than it is removed by the MAC, the QSR can be used to modify the QDR
behavior and prevent an under-run condition on the QUE. Bits 25 and 24 of the QSR are the Mode field.
The default setting for the Mode field is 00b. In this mode the QDR bit is set anytime the QUE contains at
least one BLOCK. In this mode, the host must be diligent in keeping the QUE populated with data to
avoid a TX FIFO under-run condition in the MAC.
If the Mode setting is 01b then the QDR bit for the QUE is set only when the number of BLOCKs in the
QUE is above the value indicated by the Threshold field. This will allow the host to fill the QUE up to the
threshold level at its leisure without risk of a TX FIFO under-run. The drawback to this mode is that a
small packet that uses fewer than the threshold number of BLOCKs will be stranded in the QUE until
more data is added to the QUE to bring the total number of BLOCKs up and over the threshold.
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