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參數(shù)資料
| 型號： | 78P2352-IGT/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 34/42頁 |
| 文件大小： | 0K |
| 描述： | IC LIU SDH SONET 2CH 128-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | E4，OC-3，STM1-E |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP-EP（14x14） |
| 包裝： | 管件 |
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78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 4 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
FUNCTIONAL DESCRIPTION
The 78P2352 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbps and 155.52Mbps line interfaces and
the digital universe. The chip is controllable through
pins or serial port register settings.
In hardware mode (pin control) the SPSL pin
must be low.
In software mode (SPSL pin high), control pins
are disabled and the 78P2352 must be
configured via the 4-wire serial port.
MODE SELECTION
The SDO_E4 pin or E4 register bit determines which
rate the device (both channels) operates in
according to the table below. This control, combined
with CKSL, also selects the global reference clock
frequency.
Rate
SDO_E4 pin
E4 bit
E4
High
1
STM-1, STS-3, OC-3
Low
0
The SEN_CMI pin or CMI register bit enables the
CMI encoder/decoder and selects one of two media
for reception and transmission: 75
coaxial cable in
CMI mode or optical fiber in Fiber (NRZ) mode.
Independent channel operation for media type is
available with register controls only.
Media (coding)
SEN_CMI pin
CMI bit
75
Coax (CMI)
High
1
Fiber (NRZ)
Low
0
The SDI_PAR pin or PAR register bit selects the
interface to the framer to be 4-bit parallel CMOS or
serial LVPECL.
For each interface there are
different transmit timing modes available. See
TRANSMITTER OPERATION section for more info.
REFERENCE CLOCK
The 78P2352 requires a reference clock supplied to
the CKREFP/N pins. This reference clock is used
for clock recovery in the Rx DLL and Tx DLL. It is
also used for transmit re-timing in the synchronous
transmit modes.
Refer to the TRANSMITTER
OPERATION section for timing requirements during
synchronous (re-timing) transmit modes.
For reference frequencies of 77.76MHz or lower, the
device accepts a single ended CMOS input at
CKREFP (with CKREFN grounded). For reference
frequencies of 139.264 or 155.52MHz, the device
accepts a differential LVPECL clock input at
CKREFP/N.
The frequency of this reference input is controlled by
the rate selection and the CKSL control pin or
register bit.
Reference Frequency
CKSL pin
SDO_E4 low
SDO_E4 high
Low
19.44MHz
17.408MHz
Float
77.76MHz
N/A
High
155.52MHz
139.264MHz
CKSL[1:0] bits
E4 bit = 0
E4 bit = 1
0 0
19.44MHz
17.408MHz
1 0
77.76MHz
N/A
1 1
155.52MHz
139.264MHz
RECEIVER OPERATION
The receiver accepts serial data, at 155.52Mbps or
139.264Mbps from the RXxP/N inputs. In CMI mode,
the input is differentially terminated with 75
and
transformer-coupled to a coaxial connector. In Fiber
(NRZ) mode, the input is differentially terminated
with 100
and AC-coupled to an optical transceiver
module. For board designs utilizing both coax and
fiber media options, an analog switch or mechanical
relay is required to switch between the different
terminations and media paths.
The CMI signal first enters an AGC and adaptive
equalizer
designed
to
overcome
inter-symbol
interference caused by long cable lengths.
The
variable gain differential amplifier automatically
controls the gain to maintain a constant voltage level
output regardless of the input voltage level. Note
that in Fiber (NRZ) mode, the input signals bypass
the adaptive equalizer.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a Delay Locked Loop (DLL), which
uses a reference frequency derived from the clock
applied to the CKREFP/N pins.
In serial mode, the clock and data are decoded and
transmitted through the LVPECL drivers. In parallel
mode, the data is decoded and converted into four
bit parallel segments before being transmitted
through the CMOS drivers. Note that in Fiber (NRZ)
mode, the CMI decoder is bypassed.
Receiver Monitor Mode
In CMI mode, the SCK_MON pin or MONx register
bit enables the receiver’s monitor mode which adds
approximately 20dB of flat gain to the receive signal
before equalization. Rx Monitor Mode can handle
20dB of flat loss typical of monitoring points with up
to 6dB of cable loss.
Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78P2352-IGTR | 功能描述:接口 - 專用 Dual Ch OC-3/STM1-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P2352-IGTR/F | 功能描述:接口 - 專用 Dual Ch OC-3/STM1-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P236-IP | 制造商:SSI 功能描述: |
| 78P47404T15 | 制造商:n/a 功能描述:0.47MFD 400VDC caps |
| 78P7200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Line Interface Unit |
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