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參數(shù)資料
| 型號(hào)： | 74VHC4046M |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | CMOS Phase Lock Loop |
| 中文描述： | PHASE LOCKED LOOP, 12 MHz, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 283K |
| 代理商： | 74VHC4046M |
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Detailed Circuit Description
(Continued)
means that the VCO’s frequency must be increased to bring
its leading edge into proper phase alignment. Thus the
phase detector II output is set high. This will cause the loop
filter to charge up the VCO input increasing the VCO fre-
quency. Once the leading edge of the comparator input is
detected the output goes TRI-STATE holding the VCO input
at the loop filter voltage. If the VCO still lags the signal then
the phase detector will again charge up to VCO input for the
time between the leading edges of both waveforms.
If the VCO leads the signal then when the leading edge of
the VCO is seen the output of the phase comparator goes
low. This discharges the loop filter until the leading edge of
the signal is detected at which time the output TRI-STATE
itself again. This has the effect of slowing down the VCO to
again make the rising edges of both waveform coincident.
When the PLL is out of lock the VCO will be running either
slower or faster than the signal input. If it is running slower
the phase detector will see more signal rising edges and so
the output of the phase comparator will be high a majority of
the time, raising the VCO’s frequency. Conversely, if the
VCO is running faster than the signal the output of the de-
tector will be low most of the time and the VCO’s output
frequency will be decreased.
As one can see when the PLL is locked the output of phase
comparator II will be almost always TRI-STATE except for
minor corrections at the leading edge of the waveforms.
When the detector is TRI-STATE the phase pulse output is
high. This output can be used to determine when the PLL is
in the locked condition.
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase differ-
ence between the comparator input and the signal input.
The lock range of the PLL is the same as the capture range.
Minimal power is consumed in the loop filter since in lock
the detector output is a high impedance. Also when no sig-
nal is present the detector will see only VCO leading edges,
and so the comparator output will stay low forcing the VCO
to f
min
operating frequency.
Phase comparator II is more susceptible to noise causing
the phase lock loop to unlock. If a noise pulse is seen on the
signal input, the comparator treats it as another positive
edge of the signal and will cause the output to go high until
the VCO leading edge is seen, potentially for a whole signal
input period. This would cause the VCO to speed up during
that time. When using the phase comparator I the output of
that phase detector would be disturbed for only the short
duration of the noise spike and would cause less upset.
PHASE COMPARATOR III
This comparator is a simple S-R Flip-Flop which can func-
tion as a phase comparator Figure 8. It has some similar
characteristics to the edge sensitive comparator. To see
how this detector works assume input pulses are applied to
the signal and comparator inputs as shown in Figure 9.
When the signal input leads the comparator input the flop is
set. This will charge up the loop filter and cause the VCO to
speed up, bringing the comparator into phase with the sig-
nal input. When using short pulses as input this comparator
behaves very similar to the second comparator. But one can
see that if the signal input is a long pulse, the output of the
comparator will be forced to a one no matter how many
comparator input pulses are received. Also if the VCO input
is a square wave (as it is) and the signal input is pulse then
the VCO will force the comparator output low much of the
time. Therefore it is ideal to condition the signal and com-
parator input to short pulses. This is most easily done by
using a series capacitor.
TL/F/11675–24
FIGURE 8. Phase Comparator III Logic Diagram
TL/F/11675–25
FIGURE 9. Typical Waveforms for Phase Comparator III
12
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相關(guān)代理商/技術(shù)參數(shù) |
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| 74VHC4046M | 制造商:Fairchild Semiconductor Corporation 功能描述:IC 74VHC CMOS SMD 74VHC4046 |
| 74VHC4046M_Q | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MTC | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MTCX | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MTCX_NL | 功能描述:鎖相環(huán) - PLL FINISHED GOOD RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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