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參數(shù)資料
| 型號(hào)： | 74VHC4046M |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Phase Lock Loop |
| 中文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 283K |
| 代理商： | 74VHC4046M |
Comparator I
Comparator II & III
R
2
e
%
R
2
i
%
R
2
e
%
R
2
i
%
–Given: f
0
–Use f
0
with curve titled
center frequency vs R1, C
to determine R1 and C1
–Given: f
0
and f
L
–Calculate f
min
from the
equation f
min
e
f
o
b
f
L
–Use f
min
with curve titled
offset frequency vs R2, C
to determine R2 and C1
–Calculate f
max
/f
min
from
the equation f
max
/f
min
e
f
o
a
f
L
/f
o
b
f
L
–Use f
max
/f
min
with curve
titled f
max
/f
min
vs R2/R1
to determine ratio R2/R1
to obtain R1
–Given: f
max
–Calculate f
0
from the
equation f
o
e
f
max
/2
–Use f
0
with curve titled
center frequency vs R1, C
to determine R1 and C1
–Given: f
min
and f
max
–Use f
min
with curve titled
offset frequency vs R2,
C to determine R2 and C1
–Calculate f
max
/f
min
–Use f
max
/f
min
with curve
titled f
max
/f
min
vs R2/R1
to determine ratio R2/R1
to obtain R1
(b)
FIGURE 1
(Continued)
Detailed Circuit Description
VOLTAGE CONTROLLED OSCILLATOR/SOURCE
FOLLOWER
The VCO requires two or three external components to op-
erate. These are R1, R2, C1. Resistor R1 and capacitor C1
are selected to determine the center frequency of the VCO.
R1 controls the lock range. As R1’s resistance decreases
the range of f
min
to f
max
increases. Thus the VCO’s gain
decreases. As C1 is changed the offset (if used) of R2, and
the center frequency is changed. (See typical performance
curves) R2 can be used to set the offset frequency with 0V
at VCO input. If R2 is omitted the VCO range is from 0Hz. As
R2 is decreased the offset frequency is increased. The ef-
fect of R2 is shown in the design information table and typi-
cal performance curves. By increasing the value of R2 the
lock range of the PLL is offset above 0Hz and the gain
(Volts/rad.) does not change. In general, when offset is de-
sired, R2 and C1 should be chosen first, and then R1 should
be chosen to obtain the proper center frequency.
Internally the resistors set a current in a current mirror as
shown in Figure 1. The mirrored current drives one side of
TL/F/11675–18
FIGURE 2. Logic Diagram for VCO
8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74VHC4046M | 制造商:Fairchild Semiconductor Corporation 功能描述:IC 74VHC CMOS SMD 74VHC4046 |
| 74VHC4046M_Q | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MTC | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MTCX | 功能描述:鎖相環(huán) - PLL CMOS Phase-Lock Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| 74VHC4046MTCX_NL | 功能描述:鎖相環(huán) - PLL FINISHED GOOD RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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