參數(shù)資料
型號(hào)： 74LVX163MX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Synchronous Up Counter
中文描述： LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 16-BIT UP BINARY COUNTER, PDSO16
封裝： 0.150 INCH, MS-012, SOIC-16
文件頁(yè)數(shù)： 5/8頁(yè)
文件大小： 73K
代理商： 74LVX163MX
5
www.fairchildsemi.com
7
AC Electrical Characteristics
Note 4:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr)
=
C
PD
* V
CC
* f
IN
+
I
CC
.
When the outputs drive a capacitive load, total current consumption is the sum of C
PD
, and
I
CC
which is obtained from the following formula:
C
Q0
–C
Q3
and C
TC
are the capacitances at Q0–Q3 and TC, respectively. F
CP
is the input frequency of the CP.
Symbol
Parameter
V
CC
(V)
T
A
=
25
°
C
Typ
9.0
11.3
8.3
T
A
=
40
°
C to
+
85
°
C
Min
1.0
1.0
1.0
Units
Conditions
Min
Max
14.0
17.0
12.8
Max
16.0
19.0
15.0
t
PLH
t
PHL
Propagation Delay
Time (CP–Q
n
)
2.7
ns
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
V
CC
=
Open
(Note 4)
3.3
±
0.3
ns
10.8
9.5
12.5
16.3
14.3
18.5
1.0
1.0
1.0
18.5
16.7
20.5
t
PLH
t
PHL
Propagation Delay
Time (CP–TC, Count)
2.7
ns
3.3
±
0.3
8.7
11.2
11.4
13.6
17.1
18.0
1.0
1.0
1.0
16.0
19.5
21.0
ns
t
PLH
t
PHL
Propagation Delay
2.7
ns
Time (CP–TC, Load)
14.0
11.0
13.5
21.0
17.2
20.7
1.0
1.0
1.0
24.0
20.0
23.5
3.3
±
0.3
ns
t
PLH
t
PHL
Propagation Delay
Time (CET–TC)
2.7
8.6
11.0
7.5
13.5
16.5
12.3
1.0
1.0
1.0
15.0
18.5
14.5
ns
3.3
±
0.3
ns
10.5
115
80
15.8
1.0
65
45
18.0
f
MAX
Maximum Clock
Frequency
2.7
75
50
MHz
3.3
±
0.3
80
55
130
85
4
70
50
MHz
C
IN
C
PD
Input Capacitance
10
10
pF
Power Dissipation Capacitance
23
pF
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