參數(shù)資料
型號: 74LVTH322245G
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25з Series Resistors in A Port Outputs
中文描述: LVT SERIES, QUAD 8-BIT TRANSCEIVER, TRUE OUTPUT, PBGA96
封裝: 5.50 MM, PLASTIC, MO-205, FBGA-96
文件頁數(shù): 1/6頁
文件大?。?/td> 67K
代理商: 74LVTH322245G
2002 Fairchild Semiconductor Corporation
DS500408
www.fairchildsemi.com
May 2002
Revised May 2002
7
A
74LVT322245
74LVTH322245
Low Voltage 32-Bit Transceiver with 3-STATE Outputs
and 25
Series Resistors in A Port Outputs
General Description
The LVT322245 and LVTH322245 contain thirty-two non-
inverting bidirectional buffers with 3-STATE outputs and are
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 32-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVT322245 and LVTH322245 are designed with
equivalent 25
series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH322245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The
LVT322245 and LVTH322245 are fabricated with an
advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322245)
I
Also available without bushold feature (74LVT322245)
I
Live insertion/extraction permitted
I
Power Up/Power Down high impedance provides
glitch-free bus loading
I
A Port outputs include equivalent series resistance of
25
making external termination resistors unnecessary
and reducing overshoot and undershoot
I
A Port outputs source/sink
±
12 mA
B Port outputs source/sink
32 mA/
+
64 mA
I
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
I
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Note 1:
Ordering code “G” indicates TRAYS.
Note 2:
Devices also available in TAPE and REEL. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number
74LVT322245G
(Note 1) (Note 2)
74LVTH322245G
(Note 1) (Note 2)
Package Number
BGA96A
(Preliminary)
BGA96A
Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
相關(guān)PDF資料
PDF描述
74LVTH322374GX Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs (Preliminary)
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74LVTH32952 Low Voltage 32-Bit Registered Transceiver with 3-STATE Outputs (Preliminary)
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