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參數資料
| 型號： | 74LVTH16835MEA |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary) |
| 中文描述： | LVT SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 62K |
| 代理商： | 74LVTH16835MEA |
Preliminary
2000 Fairchild Semiconductor Corporation
DS500102
www.fairchildsemi.com
May 2000
Revised May 2000
7
74LVTH16835
Low Voltage 18-Bit Universal Bus Driver
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16835 consists of 18-bit universal bus drivers
which combine D-type latches and D-type flip-flops to allow
data flow in transparent, latched, or clocked modes. Data
flow from A to Y is controlled by the output-enable (OE)
input. This device operates in the transparent mode when
the latch-enable (LE) input is HIGH. The A data is latched if
the clock (CLK) input is held at a HIGH or LOW logic level.
If LE is LOW, the A-bus data is stored in the latch/flip-flop
on the LOW-to-HIGH transition of the CLK. When OE is
HIGH, the outputs are in the high-impedance state.
The LVTH16835 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The bus driver is designed for low voltage (3.3V) V
CC
appli-
cations, but with the capability to provide a TTL interface to
a 5V environment. The LVTH16835 is fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink
32 mA/
+
64 mA
I
Latch-up performance exceeds 500 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
74LVTH16835MEA
74LVTH16835MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74LVTH16835MEA_Q | 功能描述:總線收發(fā)器 18-Bit Bus Driver Universal 3 State RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16835MEAX | 功能描述:總線收發(fā)器 UB Driver LV 18Bit 3State RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16835MTD | 功能描述:總線收發(fā)器 18-Bit Bus Driver Universal 3 State RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16835MTD_Q | 功能描述:總線收發(fā)器 18-Bit Bus Driver Universal 3 State RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16835MTDX | 功能描述:總線收發(fā)器 UB Driver LV 18Bit 3State RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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