參數(shù)資料
型號(hào): 74LVTH16500MTD
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi): 通用總線功能
英文描述: Octal Bus Transceivers With 3-State Outputs 20-PDIP -40 to 85
中文描述: LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, MO-153, TSSOP-56
文件頁(yè)數(shù): 5/7頁(yè)
文件大?。?/td> 67K
代理商: 74LVTH16500MTD
Preliminary
5
www.fairchildsemi.com
7
AC Electrical Characteristics
Note 11:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 12)
Note 12:
Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C, C
L
=
50 pF, R
L
=
500
V
CC
=
3.3
±
0.3V
Min
Max
150
1.3
3.7
Units
V
CC
=
2.7V
Min
150
1.3
Max
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
MHz
Propagation Delay
4.0
ns
Data to Outputs
Propagation Delay
LEBA or LEAB to B or A
1.3
1.5
1.5
3.7
5.1
5.1
1.3
1.5
1.5
4.0
5.7
5.7
ns
Propagation Delay
CLKBA or CLKAB to B or A
Output Enable Time
1.3
1.3
1.3
5.0
5.0
4.8
1.3
1.3
1.3
5.9
5.9
5.5
ns
ns
1.3
1.7
1.7
4.8
5.8
5.8
1.3
1.7
1.7
5.5
6.3
6.3
Output Disable Time
ns
t
SU
Setup Time
A before CLKAB
2.9
2.9
ns
B before CLKBA
2.9
2.9
A or B before LE, CLK HIGH
1.4
0.5
A or B before LE, CLK LOW
2.9
2.3
t
H
Hold Time
A or B after CLK
0.4
0.4
ns
A or B after LE
LE HIGH
1.6
3.3
1.6
3.3
t
W
Pulse Duration
ns
CLK HIGH or LOW
3.3
3.3
t
OSLH
t
OSHL
Output to Output Skew (Note 11)
1.0
1.0
ns
1.0
1.0
Symbol
C
IN
C
I/O
Parameter
Conditions
Typical
4
Units
pF
Input Capacitance
V
CC
=
0V, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
Input/Output Capacitance
8
pF
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