- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄375082 > 74LVTH16500 (Fairchild Semiconductor Corporation) Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary PDF資料下載
參數(shù)資料
| 型號(hào)： | 74LVTH16500 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 中文描述： | 低電壓18位通用總線收發(fā)器與三態(tài)輸出的初步 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 67K |
| 代理商： | 74LVTH16500 |
Preliminary
www.fairchildsemi.com
2
7
Connection Diagram
Pin Descriptions
Function Table
(Note 1)
H
=
HIGH Voltage Level
X
=
Immaterial
↓
=
HIGH-to-LOW Clock Transition
Note 1:
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2:
Output level before the indicated steady-state input conditions
were established.
Note 3:
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
L
=
LOW Voltage Level
Z
=
High Impedance
Functional Description
For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the HIGH-to-LOW transition of CLKAB. Output-
enable OEAB is active-HIGH. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in
the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active-HIGH and OEBA is active-
LOW).
Logic Diagram
Pin Names
A
1
–
A
18
B
1
–
B
18
CLKAB, CLKBA Clock Pulse Inputs
LEAB, LEBA
Latch Enable Inputs
OEAB, OEBA
Output Enable Inputs
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Inputs
Output
B
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↓
↓
H
L
A
X
L
H
L
H
X
X
Z
L
H
L
H
B
0
(Note 2)
B
0
(Note 3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVTH16500MEA | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 74LVTH16500MTD | Octal Bus Transceivers With 3-State Outputs 20-PDIP -40 to 85 |
| 74LVTH16501 | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 74LVTH16501MEA | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
| 74LVTH16501MTD | Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH16500 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16500DGGRE4 | 功能描述:通用總線函數(shù) 3.3V ABT 18-Bit Univ Bus Trncvr W/3St Otp RoHS:否 制造商:Texas Instruments 邏輯類(lèi)型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16500DGGRG4 | 功能描述:通用總線函數(shù) 3.3-V ABT 18B Univ Bus Xcvr RoHS:否 制造商:Texas Instruments 邏輯類(lèi)型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開(kāi)啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16500DLRG4 | 功能描述:總線收發(fā)器 3.3V ABT 16B Univ 總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16500MEA | 功能描述:總線收發(fā)器 UB Transceiver 18Bit RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。