參數(shù)資料
型號: 74LVTH125SJX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage Quad Buffer with 3-STATE Outputs
中文描述: LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14
文件頁數(shù): 1/8頁
文件大?。?/td> 93K
代理商: 74LVTH125SJX
2005 Fairchild Semiconductor Corporation
DS012011
www.fairchildsemi.com
October 1998
Revised February 2005
7
74LVTH125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVTH125 contains four independent non-inverting
buffers with 3-STATE outputs.
These buffers are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH125 is fabricated with
an advanced BiCMOS technology to achieve high speed
operation similar to 5V ABT while maintaining a low power
dissipation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink 32 mA/ 64 mA
I
Functionally compatible with the 74 series 125
I
Latch-up performance exceeds 500 mA
I
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDED J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Number
M14A
M14D
MTC14
MTC14
Package Description
74LVTH125M
74LVTH125SJ
74LVTH125MTC
74LVTH125MTCX_NL
(Note 1)
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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