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參數資料
| 型號： | 74LVC2G06 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85 |
| 中文描述： | 四2正輸入或門 14-TSSOP封裝；-40℃到85℃ |
| 文件頁數： | 2/18頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 74LVC2G06 |
2005 Feb 02
2
Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V
tolerant inputs/outputs; 3-state
74LVC2G241
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
±
24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
40
°
C to +85
°
C and
40
°
C to +125
°
C.
DESCRIPTION
The 74LVC2G241 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G241 is a dual non-inverting buffer/line driver
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH level at
pin 1OE causes output 1Y to assume a high-impedance
OFF-state. A LOW level at pin 2OE causes output 2Y to
assume a high-impedance OFF-state. Schmitt-trigger
action at all inputs makes the circuit highly tolerant for
slower input rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay inputs nA to output nY V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
4.5
2.8
2.8
2.6
2.1
2
20
5
ns
ns
ns
ns
ns
pF
pF
pF
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
C
I
C
PD
input capacitance
power dissipation capacitance per buffer
output enabled; notes 1 and 2
output disabled; notes 1 and 2
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