參數(shù)資料
型號(hào): 74LVC169
廠商: NXP Semiconductors N.V.
英文描述: Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-PDIP -40 to 85
中文描述: 可預(yù)置同步4位向上/向下二進(jìn)制計(jì)數(shù)器
文件頁數(shù): 4/14頁
文件大?。?/td> 124K
代理商: 74LVC169
Philips Semiconductors
Product specification
74LVC169
Presettable synchronous 4-bit up/down
binary counter
1998 May 20
4
STATE DIAGRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COUNT DOWN
COUNT UP
SF00788
FUNCTION TABLE
OPERATING
MODES
INPUTS
CEP
OUTPUTS
Q
n
CP
U/D
CET
PE
D
n
TC
Parallel load
(Dn
Qn)
X
X
X
l
l
L
*
X
X
X
X
X
H
*
Count Up
(increment)
Count Down
(decrement)
h
l
l
h
X
Count
Up
Count
Down
*
l
l
l
h
X
*
Hold
(do nothing)
X
h
X
h
X
q
n
*
X
X
X
h
X
q
n
H
H = High voltage level steady state
h = High voltage level one setup time prior to the Low-to-High
clock transition
L = Low voltage level steady state
l
= Low voltage level one setup time prior to the Low-to-High
clock transition
q = Lower case letters indicate the state of the referenced output
prior to the Low-to-High clock transition
X = Don’t care
= Low-to-High clock transition
*
= The TC is Low when CET is Low and the counter is at
Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is
(LLLL).
TYPICAL TIMING SEQUENCE
CP
PE
TC
MR
INHIBIT
COUNT
CEP
CET
D0
D2
D1
D3
Q0
Q2
Q1
Q3
RESET PRESET
12
13
14
15
0
1
2
SY00069
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit
相關(guān)PDF資料
PDF描述
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