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參數(shù)資料
| 型號： | 74LV573 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal D-type transparent latch 3-State |
| 中文描述： | 八路D型透明鎖存器三態(tài) |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 74LV573 |
Philips Semiconductors
Product specification
74LV573
Octal D-type transparent latch (3-State)
1998 Jun 10
8
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5 * V
CC
at V
CC
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V and
V
X
= V
OL
+ 0.1V
CC
at V
CC
<
2.7V and
V
Y
= V
OH
– 0.3V at V
CC
2.7V and
V
Y
= V
OH
– 0.1V
CC
at V
CC
<
2.7V and
2.7V and
2.7V and
3.6V
4.5V
3.6V
4.5V
3.6V
4.5V
SV00705
V
M
D
n
INPUT
V
I
GND
V
OH
V
OL
Q
n
OUTPUT
V
M
t
PLH
t
PHL
Figure 1. Data input (D
n
) to output (Q
n
) propagation delays and
the output transition times
SV00706
V
M
LE INPUT
V
I
GND
V
OL
V
OH
Q
n
OUTPUT
V
M
t
PLH
t
PHL
t
W
Figure 2. Latch enable input (LE) pulse width, the latch enable
input to output (Q
n
) propagation delays and the output
transition times.
SV00664
outputs
disabled
outputs
enabled
outputs
enabled
t
PHZ
t
PZH
t
PZL
t
PLZ
V
X
V
Y
V
M
V
M
V
M
OE INPUT
V
I
V
CC
V
OL
V
OH
GND
GND
Q
OUTPUT
LOW-to-OFF
OFF-to-LOW
Q
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
Figure 3. 3-State enable and disable times
SV00665
ééééééééééééé
ééééééééééééé
ééééééééééééé
V
M
D
n
INPUT
LE INPUT
GND
GND
V
I
V
I
V
M
t
su
t
su
NOTE:
The shaded areas indicate when the input is permitted
to change for predictable output performance.
Figure 4. Data set-up and hold times for the D
n
input to the LE
input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance.
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
2.7V
2.7–3.6V
4.5V
V
CC
50 pF
SV00896
S
1
t
PLZ/
t
PZL
t
PHZ/
t
PZH
Open
2 * V
CC
GND
R
L
= 1k
Open
GND
2 * V
CC
Figure 5. Load circuitry for switching times
相關PDF資料 |
PDF描述 |
|---|---|
| 74LV573PWDH | Octal D-type transparent latch 3-State |
| 74LV574 | Octal D-type flip-flop; positive edge-trigger 3-State |
| 74LV574PWDH | Octal D-type flip-flop; positive edge-trigger 3-State |
| 74LV595PWDH | 8-bit serial-in/serial or parallel-out shift register with output latches 3-State |
| 74LV595 | 8-bit serial-in/serial or parallel-out shift register with output latches (3-State)(帶輸出鎖存的8位串聯(lián)輸入/串聯(lián)或并聯(lián)輸出移位寄存器（三態(tài)）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV573A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 74LV573D | 制造商:NXP Semiconductors 功能描述:74LV SMD 74LV573 SOIC20 3.3V |
| 74LV573D,112 | 功能描述:閉鎖 OCTAL TRANSPARANT LATCH RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LV573D,118 | 功能描述:閉鎖 OCTAL TRANSPARANT RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LV573D | 制造商:NXP Semiconductors 功能描述:IC SM 74LV LOGIC |
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