參數(shù)資料
型號： 74LV4316PWDH
廠商： NXP SEMICONDUCTORS
元件分類： 多路復(fù)用及模擬開關(guān)
英文描述： STANDARD GAIN HORN; WAVEGUIDE SIZE: WR34; FREQUENCY RANGE: 22.00-33.00; GAIN: 10 dB
中文描述： QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16
文件頁數(shù)： 2/16頁
文件大?。?/td> 156K
代理商： 74LV4316PWDH
Philips Semiconductors
Product specification
74LV4316
Quad bilateral switches
2
1998 Jun 23
853-2079 19619
FEATURES
Optimized for Low Voltage applications: 1.0V to 6.0V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Low typ “ON” resistance:
80 at V
CC
– VEE = 4.5V
120 at V
CC
– VEE = 3.0V
295 at V
CC
– VEE = 2.0V
Logic level translation: to enable 3V logic to communicate
with
3V analog signals
Typical “break before make” built in
Output capability: non-standard
I
CC
category: MSI
DESCRIPTION
The 74LV4316 is a low-voltage CMOS device that is pin and
function compatible with 74HC/HCT4316.
The 74LV4316 has four independent analog switches. Each switch
has two input/output terminals (nY, nZ) and an active HIGH select
input (nS). When the enable input (E) is HIGH, all four analog
switches are turned off.
Current through a switch will not cause additional V
current provided
the voltage at the terminals of the switch is maintained within the
supply voltage range; V
>
(V
, V
Z
)
>
V
. Inputs nY and nZ are
electrically equivalent terminals. V
and GND are the supply voltage
pins for the digital control inputs (E and nS). The V
CC
to GND ranges
are 1.0 to 6.0 V.
The analog inputs/outputs (nY and nZ) can swing between V
CC
as a
positive limit and V
EE
as a negative limit.
V
CC
– V
EE
may not exceed 6.0 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PZH
/t
PZL
Turn “ON” time:
E to V
OS
nS to V
OS
Turn “OFF” time:
E to V
OS
nS to V
OS
Input capacitance
Power dissipation capacitance per switch
Maximum switch capacitance
C
L
= 15pF
R
L
= 1K
V
CC
= 3.3V
19
ns
t
PHZ
/t
PLZ
20
ns
C
I
C
PD
C
S
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
V
CC
= supply voltage in V:
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
3.5
13
5
pF
pF
pF
Notes 1, 2
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°
C to +125
°
C
74LV4316 N
74LV4316 N
SOT38-4
16-Pin Plastic SO
–40
°
C to +125
°
C
74LV4316 D
74LV4316 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV4316 DB
74LV4316 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV4316 PW
74LV4316PW DH
SOT403-1
PIN CONFIGURATION
SV01650
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
GND
V
CC
1Z
1Y
2Y
2Z
2S
3S
E
1S
4S
4Z
4Y
3Y
3Z
V
EE
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 4, 10, 13
1Z – 4Z
Independent inputs/outputs
2, 3, 11, 12
1Y – 4Y
Independent inputs/outputs
7
E
Enable input (active LOW)
8
GND
Ground (0V)
9
V
EE
Negative supply voltage
15, 5, 6, 14
1S – 4S
Select inputs (active HIGH)
16
V
CC
Positive supply voltage
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