參數(shù)資料
型號： 74LV4060PWDH
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 14-stage binary ripple counter with oscillator
中文描述： LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16
封裝： 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
文件頁數(shù)： 2/18頁
文件大?。?/td> 165K
代理商： 74LV4060PWDH
Philips Semiconductors
Product specification
74LV4060
14-stage binary ripple counter with oscillator
2
1998 Jun 23
853-2076 19619
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25 C.
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V, T
amb
= 25 C.
All active components on chip
RC or crystal oscillator configuration
Output capability: standard (except for R
TC
and C
TC
)
I
CC
category: MSI
APPLICATIONS
Control Counters
Timers
Frequency Dividers
Time-delay circuits
DESCRIPTION
The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT4060.
The 74LV4060 is a 14-stage ripple-carry counter/divider and
oscillator with three oscillator terminals (RS, R
TC
and C
TC
), ten
buffered outputs (Q
3
to Q
9
and Q
11
to Q
13
) and an overriding
asynchronous master reset (MR). The oscillator configuration allows
design of either RC or crystal oscillator circuits. The oscillator may
be replaced by an external clock signal at input RS. In this case,
keep the oscillator pins (R
TC
and C
TC
) floating.
The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q
3
to Q
9
and Q
11
to
Q
13
= LOW), independent of the other input conditions.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 C; t
r
= t
f
<
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
C
L
= 15 pF
V
CC
=
3.3 V
RS to Q
3
Q
n
to Q
n+1
MR to Q
n
Maximum clock frequency
29
t
PHL
/t
PLH
t
PHL
f
max
6
ns
16
99
MHz
C
1
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per package
Notes 1, 2 and 3
40
pF
NOTES:
1. C
PD
is used to determine the dynamic power
dissipation (P
in W)
P
= C
x V
D
x f
+ (C
L
x V
CC2
x f
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
(C
x V
CC2
x f
o
) = sum of the outputs.
2. The condition is V
= GND to V
3. For formula on dynamic power dissipation, see the
following pages.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°
C to +125
°
C
74LV4060 N
74LV4060 N
SOT38-4
16-Pin Plastic SO
–40
°
C to +125
°
C
74LV4060 D
74LV4060 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV4060 DB
74LV4060 DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV4060 PW
74LV4060PW DH
SOT403-1
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