參數資料
型號： 74LV4060
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： 14-stage binary ripple counter with oscillator(帶振蕩器的14級二進制紋波計數器)
中文描述： 14級的振蕩器（帶振蕩器的14級二進制紋波計數器二進制紋波計數器）
文件頁數： 9/18頁
文件大?。?/td> 165K
代理商： 74LV4060
Philips Semiconductors
Product specification
74LV4060
14-stage binary ripple counter with oscillator
1998 Jun 23
9
SYMBOL
UNIT
LIMITS
TEST CONDITIONS
PARAMETER
-40
°
C to +125
°
C
-40
°
C to +85
°
C
V
CC
= 1.2V; V
I
= V
IH
and V
I
= V
IL;
–I
O
= 6mA
V
CC
= 2.0V; V
I
= V
IH
and V
I
= V
IL;
–I
O
= 6mA
V
CC
= 2.7V; V
I
= V
IH
and V
I
= V
IL;
–I
O
= 6mA
V
CC
= 3.0V; V
I
= V
IH
and V
I
= V
IL;
–I
O
= 6mA
V
CC
= 4.5V; V
I
= V
IH
and V
I
= V
IL;
–I
O
= 6mA
–
–
–
–
–
HIGH level output
HIGH level out ut
voltage;
except R
TC
and
C
TC
outputs
–
–
–
–
–
V
OL
–
0.25
0.40
–
0.50
V
–
–
–
–
–
–
–
–
–
–
I
I
Input leakage
current
Quiescent supply
current
Quiescent supply
current
Additional
quiescent supply
current per input
pin
V
CC
= 5.5V; V
I
= V
CC
or GND
–
–
1.0
–
1.0
μ
A
I
CC
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
–
–
20
–
160
μ
A
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
–
–
–
–
80
I
CC
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V;
I
O
–
–
500
–
850
μ
A
NOTE:
1. All typical values are measured at T
amb
= 25
°
C.
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
= 2.5ns; C
L
= 50pF; R
L
= 500
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°
C
TYP
1
180
52
42
33
2
24
40
14
10
8
2
6
100
29
24
19
2
14
9
6
5
4
10
8
6
4
LIMITS
–40 to +125
°
C
MIN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
38
30
24
20
38
30
24
20
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
MIN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
34
25
20
16
34
25
20
16
MAX
–
84
66
53
39
–
23
16
13
9
–
46
39
31
23
–
–
–
–
–
–
–
–
MAX
–
105
83
66
49
–
29
20
16
11
–
58
49
39
29
–
–
–
–
–
–
–
–
Propagation delay
RS to Q
3
t
PHL/
t
PLH
Figures, 6, 8
ns
Propagation delay
n
n+1
Q
to Q
t
PHL/
t
PLH
Figures 7, 8
ns
Propagation delay
MR to Q
n
t
PHL
Figures 7, 8
ns
t
W
Clock pulse width
RS; HIGH or LOW
Figure 6
ns
t
W
Master reset pulse
width MR; HIGH
Figure 7
ns
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