參數(shù)資料
型號: 74LV4053PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 多路復(fù)用及模擬開關(guān)
英文描述: Triple 2-channel analog multiplexer/demultiplexer
中文描述: TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16
封裝: PLASTIC, TSSOP-16
文件頁數(shù): 8/16頁
文件大小: 154K
代理商: 74LV4053PWDH
Philips Semiconductors
Product specification
74LV4053
Triple 2-channel analog multiplexer/demultiplexer
1998 Jun 23
8
ADDITIONAL AC CHARACTERISTICS
Recommended conditions and typical values
GND = 0 V; t
r
= t
f
2.5ns
SYMBOL
PARAMETER
TYP.
UNIT
V
CC
(V)
3.0
6.0
3.0
6.0
3.0
6.0
3.0
6.0
3.0
6.0
V
is(p–p)
(V)
2.75
5.50
2.75
5.50
Note 1
CONDITIONS
Sine-wave distortion
f = 1 kHz
Sine-wave distortion
f = 10 kHz
Switch “OFF” signal feed through
0.80
0.40
2.40
1.20
–50
–50
–60
–60
110
120
%
R
= 10 k ; C
= 50 pf
Figures 9 and 10
R
= 10 k ; C
= 50 pf
Figures 9 and 10
R
= 600 ; C
= 50 pf; f= 1 MHz
Figures 5 and 11
R
= 600 ; C
L
= 50 pf; f= 1 MHz
Figure 8
R
L
= 600 ; C
= 50 pf; f= 1 MHz
(S
n
or E, square wave between V
CC
and GND t
r
= t
f
= 6 ns) Figure 8
R
L
= 50 ; C
L
= 50 pF
Figures 6, 8 and 9
%
dB
Crosstalk between any two
switches/multiplexers
Crosstalk voltage between enable or
address input to any switch
(peak-to-peak value)
Minimum frequency response
(–3 dB)
Maximum switch capacitance
GENERAL NOTES:
V
is
is the input voltage at nY
or nZ terminal, whichever is assigned as an input.
V
is the output voltage at nY
n
or nZ terminal, whichever is assigned as an output.
NOTES:
1.
Adjust input voltage V
is
is 0 dBm level (0 dBm = 1 mW into 600
2.
Adjust input voltage V
is
is 0 dBm level at V
OS
for 1 MHz (0 dBm = 1 mW into 50
dB
Note 1
V
(p–p)
mV
f
max
180
200
5
MHz
3.0
6.0
Note 2
C
S
pf
SV01635
(dB)
f (kHz)
0
10
10
2
10
3
10
4
10
5
10
6
–50
–100
Figure 6. Typical switch “OFF” signal feed-through as a
function of frequency.
SV01636
(dB)
f (kHz)
5
10
10
2
10
3
10
4
10
5
10
6
0
–5
Figure 7. Typical frequency response.
NOTES TO FIGURES 6 AND 7:
Test conditions: V
CC
= 3.0 V; GND = 0 V; V
EE
= -3.0V; R
L
= 50 ; R
SOURCE
= 1k .
SV01663
GND
2R
L
V
CC
channel
ON
Vis
0.1 F
R
L
nY
n
/nZ
nZ/nY
n
C
L
GND
channel
OFF
(b)
(a)
V
os
dB
2R
L
nY
n
/nZ
2R
L
2R
L
V
CC
V
CC
nZ/nY
n
2R
L
C
L
R
L
Figure 8. Test circuit for measuring crosstalk between any two switches.
(a) channel ON condition; (b) channel OFF condition.
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