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參數(shù)資料
| 型號： | 74LV393PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-bit binary ripple counter |
| 中文描述： | LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14 |
| 封裝： | PLASTIC, SOT-402, TSSOP1-14 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74LV393PWDH |
Philips Semiconductors
Product specification
74LV393
Dual 4-bit binary ripple counter
2
1998 Jun 10
853–1936 19545
FEATURES
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Two 4-bit binary counters with individual clocks
Divide-by any binary module up to 28 in one package
Two master resets to clear each 4-bit counter individually
Output capability: standard
I
CC
category: MSI
0.8V @ V
CC
= 3.3V,
2V @ V
CC
= 3.3V,
DESCRIPTION
The 74LV393 is a low–voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT393.
The 74LV393 is a dual 4-bit binary ripple counter with separate
clocks (1CP, 2CP) and master reset (1MR, 2MR) inputs to each
counter.
The operation of each half of the ‘‘393’’ is the same as the ‘‘93’’
except no external clock connections are required. The counters are
triggered by a HIGH-to-LOW transition of the clock inputs. The
counter outputs are internally connected to provide clock inputs to
succeeding stages. The outputs of the ripple counter do not change
synchronously and should not be used for high-speed address
decoding.
The master resets are active-HIGH asynchronous inputs to each
4-bit counter identified by the ‘‘1’’ and ‘‘2’’ in the pin description.
A HIGH level on the nMR input overrides the clock and sets the
outputs LOW.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nCP to nQ
0
nQ to nQn+1
nMR to nQn
C
L
= 15pF
V
CC
= 3.3V
12
4
11
ns
f
max
C
I
C
PD
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
= C
V
CC2
f
(C
L
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
Maximum clock frequency
99
MHz
Input capacitance
3.5
pF
Power dissipation capacitance per flip-flop
V
I
= GND to V
CC
1
23
pF
V
CC2
f
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
74LV393 N
74LV393 N
SOT27-1
14-Pin Plastic SO
74LV393 D
74LV393 D
SOT108-1
14-Pin Plastic SSOP Type II
74LV393 DB
74LV393 DB
SOT337-1
14-Pin Plastic TSSOP Type I
74LV393 PW
74LV393PW DH
SOT402-1
PIN CONFIGURATION
SV00672
1CP
1MR
1Q
0
1Q
2
1Q
3
GND
V
CC
2CP
2MR
2Q
0
2Q
1
2Q
2
2Q
3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Q
1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 13
1CP, 2CP
Clock inputs
(HIGH-to-LOW, edge-triggered)
2, 12
1MR, 2MR
Asynchronous master reset inputs
(active HIGH)
3, 4, 5, 6
11, 10, 9, 8
1Q
0
to 1Q
3
2Q
0
to 2Q
3
Flip-flop outputs
7
GND
Ground (0V)
14
V
CC
Positive supply voltage
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