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參數(shù)資料
| 型號(hào)： | 74LCXU04MTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW VOLTAGE CMOS HEX INVERTER(SINGLE STAGE) WITH 5V TOLERANT INPUTS |
| 中文描述： | 低電壓CMOS六角逆變器（單場(chǎng)）5V容限輸入 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 204K |
| 代理商： | 74LCXU04MTR |
74LCXU04
4/11
Table 8: AC Electrical Characteristics
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/6 (per gate)
Figure 3: Test Circuit
C
L
= 50 pF or equivalent (includes jig and probe capacitance)
R
L
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
=
t
r
(ns)
-40 to 85 °C
-55 to 125 °C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
2.7
50
500
2.5
6.0
5.2
1.0
6.0
5.2
1.0
ns
3.0 to 3.6
3.0 to 3.6
1.0
1.0
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
50
500
2.5
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 °C
Min.
Typ.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(note 1)
3.3
3.3
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
6
50
pF
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LCXU04TTR | LOW VOLTAGE CMOS HEX INVERTER(SINGLE STAGE) WITH 5V TOLERANT INPUTS |
| 74LS00N | QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
| 74LS00N | Quad 2-Input NAND Gate |
| 74LS00N | QUAD 2-INPUT NAND GATE |
| 74LS00 | QUAD 2-INPUT NAND GATE |
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