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參數(shù)資料
| 型號： | 74LCX74TTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTS |
| 中文描述： | 低電壓CMOS雙D型觸發(fā)器與5V容限輸入 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 84K |
| 代理商： | 74LCX74TTR |
74LCX74
5/11
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value ofthe difference between the actual propagation delayfor anytwo outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
Flip-Flop)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
=
t
r
(ns)
-40 to 85
°
C
-55 to 125
°
C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time (CK to Q or Q)
2.7
50
500
2.5
1.5
1.5
1.5
8.0
7.0
8.0
1.5
1.5
1.5
9.2
8.0
9.2
ns
3.0 to 3.6
2.7
t
PLH
t
PHL
Propagation Delay
Time (PR or CLR to
Q or Q)
Setup Time, HIGH or
LOW level D to CK
50
500
2.5
ns
3.0 to 3.6
1.5
7.0
1.5
8.0
t
S
2.7
50
500
2.5
2.5
2.5
1.5
1.5
3.0
3.5
3.5
1.5
1.5
4.0
ns
3.0 to 3.6
2.7
3.0 to 3.6
2.7
t
h
Hold Time, HIGH or
LOW level D to CK
50
500
2.5
ns
t
W
CK Pulse Width,
HIGH or LOW
PR or CLR Pulse
Width, LOW
Recovery Time PR
or CLR to CK
50
500
2.5
ns
3.0 to 3.6
3.0
4.0
t
rec
2.7
50
500
2.5
0
0
0
0
ns
3.0 to 3.6
f
MAX
Clock Pulse
Frequency
Output ToOutput
Skew Time (note1,
2)
2.7
50
500
2.5
150
150
MHz
t
OSLH
t
OSHL
3.0 to 3.6
50
500
2.5
1.0
1.0
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
°
C
Min.
Typ.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(note 1)
3.3
3.3
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
6
pF
40
pF
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