參數(shù)資料
型號(hào): 74LCX74MTR
廠商: 意法半導(dǎo)體
英文描述: LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTS
中文描述: 低電壓CMOS雙D型觸發(fā)器與5V容限輸入
文件頁(yè)數(shù): 1/11頁(yè)
文件大?。?/td> 84K
代理商: 74LCX74MTR
1/11
September 2001
I
5V TOLERANT INPUTS
HIGH SPEED :
f
MAX
= 150 MHz (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
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DESCRIPTION
The 74LCX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.
A signal on the D INPUT is transferred to the Q
OUTPUT duringthe positive going transitionof the
clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All
inputs
and
outputs
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
are
equipped
with
74LCX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
TSSOP
74LCX74M
74LCX74MTR
74LCX74TTR
TSSOP
SOP
相關(guān)PDF資料
PDF描述
74LCX74TTR LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTS
74LCX74 Low Voltage CMOS Dual D-Type Flip Flop with 5V Tolerant Inputs(低壓CMOS雙D觸發(fā)器)
74LCX86 Low Voltage CMOS Quad Exclusive Or Gate with 5V Tolerant Inputs(低壓CMOS四異或門(mén))
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