參數(shù)資料
型號: 74LCX573MTCX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
中文描述: LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝: 4.40 MM, MO-153AC, TSSOP-20
文件頁數(shù): 2/12頁
文件大小: 553K
代理商: 74LCX573MTCX
www.fairchildsemi.com
2
7
Logic Symbol
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Truth Table
H
HIGH Voltage
L
LOW Voltage
Z
High Impedance
X
Immaterial
O
0
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Functional Description
The LCX573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
D
0
D
7
LE
Data Inputs
Latch Enable Input
OE
3-STATE Output Enable Input
O
0
O
7
3-STATE Latch Outputs
Inputs
Outputs
OE
LE
D
O
n
L
H
H
H
L
H
L
L
L
L
X
O
0
Z
H
X
X
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