參數(shù)資料
型號: 74LCX00SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
中文描述: LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: 5.30 MM, EIAJ TYPE2, SOP-14
文件頁數(shù): 4/9頁
文件大小: 168K
代理商: 74LCX00SJ
74LCX00
4/8
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) C
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/4 (per gate)
TEST CIRCUIT
C
L
= 50 pF or equivalent (includes jig and probe capacitance)
R
L
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
=
t
r
(ns)
-40 to 85 °C
-55 to 125 °C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
2.7
50
500
2.5
5.1
4.3
1.0
5.1
4.3
1.0
ns
3.0 to 3.6
3.0 to 3.6
1.0
1.0
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
50
500
2.5
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 °C
Min.
Typ.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(note 1)
3.3
3.3
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
6
35
pF
pF
相關(guān)PDF資料
PDF描述
74LCX00M Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
74LCX00MTC Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
74LCX00MTCX Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
74LCX00MTCX_NL Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
74LCX00MX_NL Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
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