參數(shù)資料
型號(hào)： 74HCT9046A
廠商： NXP Semiconductors N.V.
英文描述： PLL with bandgap controlled VCO
中文描述： 鎖相環(huán)控制VCO的帶隙
文件頁(yè)數(shù)： 33/40頁(yè)
文件大?。?/td> 240K
代理商： 74HCT9046A
1999 Jan 11
33
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
PLL design example
The frequency synthesizer used in
the design example shown in Fig.34
has the following parameters:
Output frequency: 2 MHz to 3 MHz.
Frequency steps: 100 kHz.
Settling time: 1 ms.
Overshoot: <20%.
The open loop gain is:
H (s)
×
G (s) = K
p
×
K
f
×
K
o
×
K
n
and the K
u
i
1
+
where:
K
p
= phase comparator gain
K
f
= low-pass filter transfer gain
K
o
= K
v
/s VCO gain
K
n
=
1
n
divider ratio.
The programmable counter ratio K
n
can be found as follows:
f
step
f
f
step
100 kHz
The VCO is set by the values of R1,
R2 and C1; R2 = 10 k
(adjustable).
The values can be determined using
the information in Table 3.
With f
c
= 2.5 MHz and f
L
= 500 kHz
this gives the following values
(V
CC
= 5.0 V):
R1 = 30 k
.
R2 = 30 k
.
C1 = 100 pF.
The VCO gain is:
------
f
×
K
o
×
×
K
n
×
×
K
p
K
f
K
o
K
n
------------------K
=
N
min
f
2 MHz
20
=
=
=
N
max
-----------
-3 MHz
30
=
=
=
K
v
2f
–
π
)
1.1
V
CC
1.1
–
--------------------------2
2.8
1 MHz
2
π
×
2.24
10
6
×
r s
V
≈
=
=
The gain of the phase comparator
PC2 is:
Using PC2 with the passive filter as
shown in Fig.34 results in a high gain
loop with the same performance as a
loop with an active filter. Hence loop
filter equations as for a high gain loop
should be used. The current source
output of PC2 can be simulated then
with a fictive filter resistance:
R
b
17
The transfer functions of the filter is
given by:
1
s
τ
2
+
s
τ
2
Where:
τ
1
= R3'
×
C2.
τ
2
= R4
×
C2.
The characteristic equation is:
1
K
p
K
f
K
o
+
This results in:
+
or:
This can be written as:
s
2
2
ζω
n
s
+
with the natural frequency
ω
n
defined
×
1
as:
and the
damping value given as:
ζ
0.5
τ
2
=
In Fig.35 the output frequency
response to a step of input frequency
is shown.
The overshoot and settling time
percentages are now used to
determine
ω
n
. From Fig.35 it can be
K
p
×
4
π
---5
0.4V r
=
=
R3'
------
=
K
f
-----------------
=
×
×
K
n
×
1
K
p
1
-----------------
s
τ
2
+
s
τ
1
K
-----K
n
s
0
=
s
2
sK
p
K
v
K
n
τ
2
τ
1
----
K
p
K
v
K
n
τ
1
0
=
+
+
ω
n
(
)
2
+
0
=
ω
n
K
-------------------------------
K
K
n
×
=
ω
n
×
×
seen that the damping ratio
ζ
= 0.707
will produce an overshoot of less than
20% and settle to within 5% at
ω
n
t = 5.
The required settling time is 1 ms.
This results in:
5
t-
0.001
Rewriting the equation for natural
frequency results in:
K
K
K
n
ω
n
The maximum overshoot occurs at
N
max
= 30; hence K
n
=
1
30
:
When C2 = 470 nF, it follows:
τ
1
C2
470
Hence the current source bias
resistance R
b
= 17
×
2550 = 43 k
.
With
ζ
= 0.707 (0.5
× τ
2
× ω
n
) it
follows:
5000
×
τ
2
C2
470
For extra ripple suppression a
capacitor C3 can be connected in
parallel with R4, with an extra
τ
3
= R4
×
C3.
For stability reasons
τ
3
should be
<
0.1
τ
2
, hence C3
<
0.1C2, or
C3 = 39 nF.
ω
n
------5
5
10
3
×
r s
=
=
=
τ
1
(
)
2
-------------------------------
=
τ
1
0.4
2.24
×
10
6
30
×
5000
2
×
0.0012
=
=
R3'
-------
×
10
9
–
-----0.0012
2550
=
=
=
τ
2
0.5
0.00028
=
=
R4
-------
×
10
9
–
--0.00028
600
=
=
=
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74HCT9046AD 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HCT9046AD,112 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HCT9046AD,118 功能描述:鎖相環(huán) - PLL PLL BAND GAP CNTRL W/VCO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HCT9046AD-T 制造商:PHILIPS-SEMI 功能描述:
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