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參數(shù)資料
| 型號(hào)： | 74HCT573 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85 |
| 中文描述： | 八路D型透明鎖存器，三態(tài) |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 61K |
| 代理商： | 74HCT573 |
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
FEATURES
Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors
Useful as input or output port for
microprocessors/microcomputers
3-state non-inverting outputs for
bus oriented applications
Common 3-state output enable
input
Functionally identical to the “563”
and “373”
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at
the D
n
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF; V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
D
n
to Q
n
LE to Q
n
input capacitance
power dissipation capacitance per latch notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
14
15
3.5
26
17
15
3.5
26
ns
ns
pF
pF
C
I
C
PD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74HC573 | Octal D-type transparent latch; 3-state |
| 74HCT573PW | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-PDIP -40 to 85 |
| 74HC573 | Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS) |
| 74HCT574 | 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SO -40 to 85 |
| 74HC574 | Octal D-type flip-flop; positive edge-trigger; 3-state |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT573 HAR | 制造商:HAR 功能描述:74HCT573 NOTES |
| 74HCT573AN | 制造商:AVX Corporation 功能描述: |
| 74HCT573BQ | 制造商:NXP Semiconductors 功能描述:Latch Transparent 3-ST 8-CH D-Type 20-Pin DHVQFN EP T/R Cut Tape 制造商:NXP Semiconductors 功能描述:IC OCTAL D-LATCH 3-ST DHVQFN20 制造商:NXP Semiconductors 功能描述:IC, OCTAL, D-LATCH, 3-ST, DHVQFN20, Latch Type:D Type Transparent, Output Curren |
| 74HCT573BQ,115 | 功能描述:閉鎖 OCTAL LATCH RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74HCT573BQ115 | 制造商:NXP Semiconductors 功能描述: |
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