參數資料
型號： 74HCT563
廠商： NXP Semiconductors N.V.
元件分類： 通用總線功能
英文描述： 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85
中文描述： 八路D型透明鎖存器，三態(tài);反相
文件頁數： 2/7頁
文件大小： 63K
代理商： 74HCT563
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT563
FEATURES
3-state inverting outputs for bus
oriented applications
Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessor
Common 3-state output enable
input
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT563 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT563 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and inverting 3-state outputs for bus
oriented applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “563” is functionally identical to
the “573”, but has inverted outputs.
The “563” consists of eight D-type
transparent latches with 3-state
inverting outputs. The LE and OE are
common to all latches.
When LE is HIGH, data at the D
n
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
for HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
C
I
C
PD
propagation delay D
n
, LE to Q
n
input capacitance
power dissipation capacitance per latch
C
L
= 15 pF; V
CC
= 5 V
14
3.5
19
16
3.5
19
ns
pF
pF
notes 1 and 2
相關PDF資料
PDF描述
74HC563 Octal D-type transparent latch; 3-state; inverting
74HC563PW Octal D-type transparent latch; 3-state; inverting
74HC563DB Octal D-type transparent latch; 3-state; inverting
74HCT564 4-Bit Synchronous Up/Down Counters (Dual Clock With Clear) 16-SOIC -40 to 85
74HC564 Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
相關代理商/技術參數
參數描述
74HCT563D 功能描述:閉鎖 OCTAL TRANSPARANT LATCH 3-S RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74HCT563D,652 功能描述:閉鎖 OCTAL TRANSPARANT RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74HCT563D,653 功能描述:閉鎖 OCTAL TRANSPARANT RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74HCT563D653 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述:
74HCT563DB 功能描述:閉鎖 OCTAL TRANSPARANT LATCH 3-S RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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