參數(shù)資料
型號： 74HCT4052
廠商： NXP Semiconductors N.V.
英文描述： Dual 4-channel analog multiplexer/demultiplexer(雙四通道模擬多路復用器/多路分解器)
中文描述： 雙4通道模擬多路復用器/解復用器（雙四通道模擬多路復用器/多路分解器）
文件頁數(shù)： 2/15頁
文件大小： 129K
代理商： 74HCT4052
December 1990
2
Philips Semiconductors
Product specification
Dual 4-channel analog
multiplexer/demultiplexer
74HC/HCT4052
FEATURES
Wide analog input voltage range:
±
5 V.
Low “ON” resistance:
80
(typ.) at V
CC
V
EE
= 4.5 V
70
(typ.) at V
CC
V
EE
= 6.0 V
60
(typ.) at V
CC
V
EE
= 9.0 V
Logic level translation:
to enable 5 V logic to communicate
with
±
5 V analog signals
Typical “break before make” built in
Output capability: non-standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4052 are high-speed Si-gate CMOS
devices and are pin compatible with the “4052” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4052 are dual 4-channel analog
multiplexers/demultiplexers with common select logic.
Each multiplexer has four independent inputs/outputs (nY
0
to nY
3
) and a common input/output (nZ). The common
channel select logics include two digital select inputs (S
0
and S
1
) and an active LOW enable input (E).
With E LOW, one of the four switches is selected (low
impedance ON-state) by S
0
and S
1
. With E HIGH, all
switches are in the high impedance OFF-state,
independent of S
0
and S
1
.
V
CC
and GND are the supply voltage pins for the digital
control inputs (S
0
and S
1
, and E). The V
CC
to GND ranges
are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The
analog inputs/outputs (nY
0
to nY
3
, and nZ) can swing
between V
CC
as a positive limit and V
EE
as a negative limit.
V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to GND (typically ground).
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
{(C
L
+
C
S
)
×
V
CC2
×
f
o
)} where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
{(C
L
+C
S
)
×
V
CC2
×
f
o
)} = sum of outputs
C
L
= output load capacitance in pF
C
S
= max. switch capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PZH
/ t
PZL
t
PHZ
/ t
PLZ
C
I
C
PD
turn “ON” time E or S
n
to V
OS
turn “OFF” time E or S
n
to V
OS
input capacitance
power dissipation capacitance per switch notes 1 and 2
max. switch capacitance
independent (Y)
common
(Z)
C
L
= 15 pF ; R
L
= 1 k
;
V
CC
= 5 V
28
21
3.5
57
18
13
3.5
57
ns
ns
pF
pF
C
S
5
12
5
12
pF
pF
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