參數(shù)資料
型號: 74HCT40105PW
廠商: NXP SEMICONDUCTORS
元件分類: FIFO
英文描述: 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
中文描述: 16 X 4 OTHER FIFO, 120 ns, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16
文件頁數(shù): 2/25頁
文件大小: 200K
代理商: 74HCT40105PW
1998 Jan 23
2
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
FEATURES
Independent asynchronous inputs and outputs
Expandable in either direction
Reset capability
Status indicators on inputs and outputs
3-state outputs
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40105 are high-speed Si-gate CMOS
devices and are pin compatible with the “40105” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40105 are first-in/first-out (FIFO) “elastic”
storage registers that can store sixteen 4-bit words. The
“40105” is capable of handling input and output data at
different shifting rates. This feature makes it particularly
useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop,
which stores a marker bit. A “1” signifies that the position’s
data is filled and a “0” denotes a vacancy in that position.
The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the
succeeding flip-flop. When a control flip-flop is in the “0”
state and sees a “1” in the preceding flip-flop, it generates
a clock pulse that transfers data from the preceding four
data latches into its own four data latches and resets the
preceding flip-flop to “0”. The first and last control flip-flops
have buffered outputs. Since all empty locations “bubble”
automatically to the input end, and all valid data ripples
through to the output end, the status of the first control
flip-flop (data-in ready output - DIR) indicates if the FIFO is
full, and the status of the last flip-flop (data-out ready
output - DOR) indicates if the FIFO contains data. As the
earliest data is removed from the bottom of the data stack
(output end), all data entered later will automatically ripple
toward the output.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz.
f
o
= output frequency in MHz.
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5
2.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
MR to DIR, DOR
SO to Q
n
propagation delay
SI to DIR
SO to DOR
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
16
37
15
35
ns
ns
t
PHL
16
17
33
3.5
134
18
18
31
3.5
145
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
相關PDF資料
PDF描述
74HC40105 4-bit x 16-word FIFO register
74HCT4015 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
74HC4015 Dual 4-bit serial-in/parallel-out shift register
74HCT4016 Quad bilateral switches(四雙向開關)
74HC4016 Quad bilateral switches
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