參數(shù)資料
型號: 74HCT194
廠商: NXP Semiconductors N.V.
英文描述: 4-bit bidirectional universal shift register
中文描述: 4位雙向通用移位寄存器
文件頁數(shù): 2/10頁
文件大小: 79K
代理商: 74HCT194
December 1990
2
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74HC/HCT194
FEATURES
Shift-left and shift-right capability
Synchronous parallel and serial data transfer
Easily expanded for both serial and parallel operation
Asynchronous master reset
Hold (“do nothing”) mode
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT194 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The functional characteristics of the 74HC/HCT194 4-bit
bidirectional universal shift registers are indicated in the
logic diagram and function table. The registers are fully
synchronous.
The “194” design has special features which increase the
range of application. The synchronous operation of the
device is determined by the mode select inputs (S
0
, S
1
).
As shown in the mode select table, data can be entered
and shifted from left to right (Q
0
Q
1
Q
2
, etc.) or, right
to left (Q
3
Q
2
Q
1
, etc.) or parallel data can be
entered, loading all 4 bits of the register simultaneously.
When both S
0
and S
1
are LOW, existing data is retained in
a hold (“do nothing”) mode. The first and last stages
provide D-type serial data inputs (D
SR
, D
SL
) to allow
multistage shift right or shift left data transfers without
interfering with parallel load operation.
Mode select and data inputs are edge-triggered,
responding only to the LOW-to-HIGH transition of the
clock (CP). Therefore, the only timing restriction is that the
mode control and selected data inputs must be stable one
set-up time prior to the positive transition of the clock
pulse.
The four parallel data inputs (D
0
to D
3
) are D-type inputs.
Data appearing on the D
0
to D
3
inputs, when S
0
and S
1
are
HIGH, is transferred to the Q
0
to Q
3
outputs respectively,
following the next LOW-to-HIGH transition of the clock.
When LOW, the asynchronous master reset (MR)
overrides all other input conditions and forces the Q
outputs LOW.
The “194” is similar in operation to the “195” universal shift
register, with added features of shift-left without external
connections and hold (“do nothing”) modes of operation.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
= (C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
CP to Q
n
MR to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
14
11
102
3.5
40
15
15
77
3.5
40
ns
ns
MHz
pF
pF
t
PHL
f
max
C
I
C
PD
notes 1 and 2
相關(guān)PDF資料
PDF描述
74HC194 4-bit bidirectional universal shift register
74HCT195 4-bit parallel access shift register
74HC195 4-bit parallel access shift register
74HCT1G14 Inverting Schmitt-trigger(反相施密特觸發(fā)器)
74HCT1G66 Bilateral switch(雙向開關(guān))
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