參數(shù)資料
型號： 74HCT181N
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 4-bit arithmetic logic unit
中文描述： HCT SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDIP24
封裝： 0.600 INCH, PLASTIC, SOT-101-1, DIP-24
文件頁數(shù)： 10/20頁
文件大?。?/td> 165K
代理商： 74HCT181N
1998 Jun 10
10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Note to the AC characteristics
1.
For the open drain output (A=B) only t
THL
is valid.
t
PHL
/ t
PLH
propagation delay
A
i
to F
i
74
27
22
83
30
24
80
29
23
80
29
23
77
28
22
85
31
25
80
29
23
88
32
26
83
30
24
85
31
25
77
28
22
88
32
26
19
7
6
230
46
39
255
51
43
235
47
40
235
47
40
235
47
40
255
51
43
245
49
42
270
54
46
255
51
43
265
53
45
240
48
41
275
55
47
75
15
13
290
58
49
320
64
54
295
59
50
295
59
50
295
59
50
320
64
54
305
61
52
340
68
58
320
64
54
330
66
56
300
60
51
345
69
59
95
19
16
345
69
59
385
77
65
355
71
60
355
71
60
355
71
60
385
77
65
370
74
63
405
81
69
385
77
65
400
80
68
360
72
61
415
83
71
110
22
19
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
logic
M = 4.5 V;
Fig.8;
Table 3
M = 4.5 V;
Fig.8;
Table 3
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.8; Table 1
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.8; Table 1
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.10; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.10; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.11; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.11; Table 2
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
note ;
Figs 7 and 11
t
PHL
/ t
PLH
propagation delay
B
i
to F
i
ns
logic
t
PHL
/ t
PLH
propagation delay
A
n
to C
n+4
ns
sum
t
PHL
/ t
PLH
propagation delay
B
n
to C
n+4
ns
sum
t
PHL
/ t
PLH
propagation delay
A
n
to C
n+4
ns
diff
t
PHL
/ t
PLH
propagation delay
B
n
to C
n+4
ns
diff
t
PZL
/ t
PLZ
propagation delay
A
n
to A=B
ns
diff
t
PZL
/ t
PLZ
propagation delay
B
n
to A=B
ns
diff
t
PHL
/ t
PLH
propagation delay
A
n
to F
n
ns
sum
t
PHL
/ t
PLH
propagation delay
B
n
to F
n
ns
sum
t
PHL
/ t
PLH
propagation delay
A
n
to F
n
ns
diff
t
PHL
/ t
PLH
propagation delay
B
n
to F
n
ns
diff
t
THL
/ t
TLH
output transition
time
ns
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
MODE
OTHER
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
相關PDF資料
PDF描述
74HC181 4-bit arithmetic logic unit
74HC181D 4-bit arithmetic logic unit
74HC181N 4-bit arithmetic logic unit
74HCT181 4-bit arithmetic logic unit
74HCT181D 4-bit arithmetic logic unit
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