參數(shù)資料
型號(hào)： 74HCT181
廠商： NXP Semiconductors N.V.
英文描述： 4-bit arithmetic logic unit
中文描述： 4位算術(shù)邏輯單元
文件頁數(shù)： 13/20頁
文件大小： 165K
代理商： 74HCT181
1998 Jun 10
13
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
t
PHL
/ t
PLH
propagation
delay
A
i
to F
i
propagation
delay
B
i
to F
i
propagation
delay
A
i
to F
i
propagation
delay
B
i
to F
i
propagation
delay
A
n
to C
n+4
propagation
delay
B
n
to C
n+4
propagation
delay
A
n
to C
n+4
propagation
delay
B
n
to C
n+4
propagation
delay
A
n
to A=B
propagation
delay
B
n
to A=B
propagation
delay
A
n
to F
n
propagation
delay
B
n
to F
n
33
57
71
86
ns
4.5
diff
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = 4.5 V;
Fig.8; Table 3
t
PHL
/ t
PLH
33
57
71
86
ns
4.5
diff
t
PHL
/ t
PLH
29
54
68
81
ns
4.5
logic
t
PHL
/ t
PLH
33
54
68
81
ns
4.5
logic
M = 4.5 V;
Fig.8; Table 3
t
PHL
/ t
PLH
30
53
66
80
ns
4.5
sum
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.8; Table 1
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.8; Table 1
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.10; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.10; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.11; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.11; Table 2
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
t
PHL
/ t
PLH
31
53
66
80
ns
4.5
sum
t
PHL
/ t
PLH
30
55
69
83
ns
4.5
diff
t
PHL
/ t
PLH
34
55
69
83
ns
4.5
diff
t
PZL
/ t
PLZ
34
60
75
90
ns
4.5
diff
t
PZL
/ t
PLZ
35
60
75
90
ns
4.5
diff
t
PHL
/ t
PLH
33
56
70
84
ns
4.5
sum
t
PHL
/ t
PLH
33
56
70
84
ns
4.5
sum
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
MODE OTHER
+25
40 to +85
40 to +125
min. typ. max
.
min.
max.
min.
max.
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