參數(shù)資料
型號: 74HCT03
廠商: NXP Semiconductors N.V.
英文描述: Quad 2-input NAND gate
中文描述: 四2輸入與非門
文件頁數(shù): 5/8頁
文件大?。?/td> 55K
代理商: 74HCT03
December 1990
5
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
, except that the V
OH
values are
not valid for open drain. They are replaced by I
OZ
as given below.
Output capability: standard (open drain), excepting V
OH
I
CC
category: SSI
Voltages are referenced to GND (ground = 0 V)
Note
1.
The maximum operating output voltage (V
O(max)
) is 6.0 V.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
°
C)
TEST CONDITIONS
74HC
UNIT
V
CC
(V)
V
I
OTHER
+25
40 to +85
40 to +125
min.
typ.
max. min.
max. min.
max.
I
OZ
HIGH level output
leakage current
0.5
5.0
10.0
μ
A
2.0
to
6.0
V
IL
V
O
= V
O(max)(1)
or GND
SYMBOL PARAMETER
T
amb
(
°
C)
TEST CONDITIONS
74HC
UNIT
V
CC
(V)
WAVEFORMS
+25
40 to +85
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PZL
/
t
PLZ
propagation delay
nA, nB to nY
28
10
8
19
7
6
95
19
16
75
15
13
120
24
20
95
19
16
145
29
25
110
22
19
ns
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
THL
output transition time
ns
Fig.6
相關PDF資料
PDF描述
74HC109 Dual JK flip-flop with set and reset; positive-edge trigger
74HCT109 8-Line To 3-Line Priority Encoders 16-SOIC -40 to 85
74HC109PW Dual JK flip-flop with set and reset; positive-edge trigger
74HC112 Dual JK flip-flop with set and reset; negative-edge trigger
74HCT112 8-Line To 3-Line Priority Encoders 16-SO -40 to 85
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