參數(shù)資料
型號： 74HC7046A
廠商： NXP Semiconductors N.V.
英文描述： Phase-locked-loop with lock detector
中文描述： 鎖相回路鎖定探測器
文件頁數(shù)： 36/38頁
文件大小： 490K
代理商： 74HC7046A
December 1990
36
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PLL design example
The frequency synthesizer, used in the design example
shown in Fig.34, has the following parameters:
Output frequency: 2 MHz to 3 MHz
frequency steps : 100 kHz
settling time
overshoot
: 1 ms
:
<
20%
The open-loop gain is H (s) x G (s) = K
p
×
K
f
×
K
o
×
K
n
.
Where:
The programmable counter ratio K
n
can be found as
follows:
f
f
step
100 kHz
The VCO is set by the values of R1, R2 and C1,
R2 = 10 k
(adjustable). The values can be determined
using the information in the section “DESIGN
CONSIDERATIONS”.
With f
o
= 2.5 MHz and f
L
= 500 kHz this gives the following
values (V
CC
= 5.0 V):
R1 = 10 k
R2 = 10 k
C1 = 500 pF
The VCO gain is:
The gain of the phase comparator is:
V
4
π
×
The transfer gain of the filter is given by:
1
τ
s
+
1
τ
1
+
+
Where:
τ
1
K
p
K
f
K
o
K
n
=
=
=
=
phase comparator gain
low-pass filter transfer gain
K
v
/s VCO gain
1/n divider ratio
N
min.
----------
-2 MHz
20
=
=
=
N
max.
f
f
step
----------
100 kHz
-3 MHz
30
=
=
=
K
V
2f
–
π
0.9
×
–
V
CC
0.9
(
)
-----------------------2
3.2
1 MHz
2
π
×
2
10
6
×
r/s/v
≈
=
=
=
K
p
------------
0.4 V/r.
=
=
K
f
τ
2
(
)
s
------------------------------------
=
R3C2 and
τ
2
R4C2.
=
=
The characteristics equation is:
1
+
H (s)
×
G (s) = 0.
This results in:
1
+
----------------------------------K
+
The natural frequency
ω
n
is defined as follows:
×
K
n
1
+
and the damping value
ζ
is defined as follows:
2
ω
n
The overshoot and settling time percentages are now used
to determine
ω
n
. From Fig.35 it can be seen that the
damping ratio
ζ
= 0.8 will produce an overshoot of less
than 20% and settle to within 5% at
ω
n
t = 4.5. The required
settling time is 1 ms. This results in:
5
t-
0.001
Rewriting the equation for natural frequency results in:
K
K
K
ω
n
The maximum overshoot occurs at N
max
.:
2
×
×
5000
2
When C2 = 470 nF, then
τ
+
-----------------------------2
=
R3 is calculated using the damping ratio equation:
τ
1
C2
s
2
K
K
+
n
)
τ
2
τ
2
×
τ
1
(
K
--------------------------K
K
+
τ
1
n
)
τ
2
(
0.
=
+
ω
n
p
K
K
v
×
τ
2
(
)
˙
.
=
ζ
--1
1
-----------------------------------------------------
K
K
×
1
K
×
2
τ
2
×
+
×
.
=
ω
n
----5
5
10
3
×
r/s.
=
=
=
τ
1
τ
2
+
(
)
2
-------------------------------.
=
τ
1
τ
2
+
(
)
10
6
30
×
0.4
0.0011 s.
=
=
R4
τ
K
p
K
v
ω
n
K
n
×
ζ
1
–
×
×
×
790
.
=
R3
-------
R4
2 k
.
=
–
=
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74HC7046AD,112 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
74HC7046AD,118 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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