參數(shù)資料
型號: 74HC4510PW
廠商: NXP SEMICONDUCTORS
元件分類: 計數(shù)器
英文描述: BCD up/down counter
中文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDSO16
文件頁數(shù): 9/12頁
文件大?。?/td> 102K
代理商: 74HC4510PW
December 1990
6
Philips Semiconductors
Product specication
BCD up/down counter
74HC/HCT4510
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
69
25
20
220
44
37
275
55
47
330
66
56
ns
2.0
4.5
6.0
Fig.7
tPHL
propagation delay
MR to Qn
63
23
18
210
42
36
265
53
45
315
63
54
ns
2.0
4.5
6.0
Fig.10
tPLH/ tPHL
propagation delay
PL to Qn
77
28
22
250
50
43
315
63
54
375
75
64
ns
2.0
4.5
6.0
Fig.9
tPHL/ tPLH
propagation delay
CP to TC
74
27
22
260
52
44
325
65
55
395
78
66
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
CE to TC
36
13
10
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.8
tPLH
propagation delay
MR to TC
69
25
20
235
47
40
295
59
50
355
71
60
ns
2.0
4.5
6.0
Fig.10
tPHL/ tPLH
propagation delay
PL to TC
91
33
26
300
60
51
375
75
64
450
90
77
ns
2.0
4.5
6.0
Fig.9
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.9
tW
pulse width CP, CE
HIGH or LOW
80
16
14
25
9
7
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
tW
parallel load pulse
width
HIGH
80
16
14
22
8
7
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
tW
master reset pulse
width
HIGH
100
20
17
19
7
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.10
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