參數資料
型號: 74HC4024D,652
廠商: NXP Semiconductors
文件頁數: 2/19頁
文件大?。?/td> 0K
描述: IC COUNTER 7STAGE BINARY 14SOIC
產品培訓模塊: Logic Packages
標準包裝: 57
系列: 74HC
邏輯類型: 二進制計數器
方向:
元件數: 1
每個元件的位元數: 7
復位: 異步
計數速率: 90MHz
觸發(fā)器類型: 負邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 14-SO
包裝: 管件
產品目錄頁面: 834 (CN2011-ZH PDF)
其它名稱: 568-1448-5
74HC4024D
933714410652
74HC4024
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 31 October 2013
10 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
[1]
tpd is the same as tPLH and tPHL.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(C
L VCC
2
f
o) = sum of outputs.
12. Waveforms
fmax
maximum frequency
CP; see Figure 6
VCC = 2.0 V
4.0
--MHz
VCC = 4.5 V
20
--MHz
VCC = 6.0 V
24
--MHz
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr =tf =6 ns; CL = 50 pF; see Figure 7.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to
clock (CP) recovery time.
VM = 0.5 VI.
Fig 6.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
MR input
CP input
Q0 or Qn
output
tW
tPHL
1/fmax
trec
VM
001aab910
tPLH
tW
tTLH
tTHL
tPHL
VM
90 %
10 %
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