參數(shù)資料
型號(hào)： 74HC181D
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 4-bit arithmetic logic unit
中文描述： HC/UH SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDSO24
封裝： PLASTIC, SOT-108, SO-24
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 165K
代理商： 74HC181D
1998 Jun 10
9
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
MODE
OTHER
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
C
n
to C
n+4
55
20
16
69
25
20
72
26
21
77
28
22
76
26
21
77
28
22
61
22
18
63
23
18
55
20
16
63
23
18
77
28
22
85
31
25
77
28
22
83
31
24
165
33
28
200
40
34
210
42
36
230
46
39
215
43
37
240
48
41
185
37
31
195
39
33
170
34
29
195
39
33
230
46
39
255
51
43
235
47
40
255
51
43
205
41
35
250
50
43
265
53
45
290
58
49
270
54
46
300
60
51
230
46
39
245
49
42
215
43
37
245
49
42
290
58
49
320
64
54
295
59
50
320
64
54
250
50
43
300
60
51
315
63
54
345
69
59
320
65
55
360
72
61
280
56
48
295
59
50
255
51
43
295
59
50
345
69
59
385
77
65
355
71
60
385
77
65
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
sum
diff
M = 0 V;
Fig.9;
Tables 1 and 2
M = 0 V;
Fig.9;
Tables 1 and 2
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
1
= S
2
= 0 V;
S
0
= S
3
= 4.5 V;
Fig.7; Table 1
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
M = S
0
= S
3
= 0 V;
S
1
= S
2
= 4.5 V;
Fig.8; Table 2
t
PHL
/ t
PLH
propagation delay
C
n
to F
n
ns
sum
diff
t
PHL
/ t
PLH
propagation delay
A
n
to G
ns
sum
t
PHL
/ t
PLH
propagation delay
B
n
to G
ns
sum
t
PHL
/ t
PLH
propagation delay
A
n
to G
ns
diff
t
PHL
/ t
PLH
propagation delay
B
n
to G
ns
diff
t
PHL
/ t
PLH
propagation delay
A
n
to P
ns
sum
t
PHL
/ t
PLH
propagation delay
B
n
to P
ns
sum
t
PHL
/ t
PLH
propagation delay
A
n
to P
ns
diff
t
PHL
/ t
PLH
propagation delay
B
n
to P
ns
diff
t
PHL
/ t
PLH
propagation delay
A
i
to F
i
ns
sum
t
PHL
/ t
PLH
propagation delay
B
i
to F
i
ns
sum
t
PHL
/ t
PLH
propagation delay
A
i
to F
i
ns
diff
t
PHL
/ t
PLH
propagation delay
B
i
to F
i
ns
diff
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