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參數(shù)資料
| 型號： | 74HC175 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad D-type flip-flop with reset; positive-edge trigger |
| 中文描述： | 四D型觸發(fā)器的復(fù)位觸發(fā)器，積極邊緣觸發(fā) |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 74HC175 |
1998 Jul 08
2
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
FEATURES
Four edge-triggered D flip-flops
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT175 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT175 have four edge-triggered, D-type
flip-flops with individual D inputs and both Q and Q
outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All Q
n
outputs will be forced LOW independently of clock
or data inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true
and complement outputs are required and the clock and
master reset are common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
propagation delay
CP to Q
n
, Q
n
MR to Q
n
propagation delay
CP to Q
n
, Q
n
MR to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
17
15
16
19
ns
ns
t
PLH
17
15
83
3.5
32
16
16
54
3.5
34
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC175ADR2 | 制造商:Motorola Inc 功能描述: |
| 74HC175D | 功能描述:觸發(fā)器 QUAD D F/F POS-EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HC175D(BJ) | 功能描述:IC D-TYPE POS TRG SNGL 16SOIC 制造商:toshiba semiconductor and storage 系列:74HC 包裝:剪切帶（CT） 零件狀態(tài):在售 功能:主復(fù)位 類型:D 型 輸出類型:差分 元件數(shù):1 每元件位數(shù):4 頻率 - 時鐘:63MHz 不同 V，最大 CL 時的最大傳播延遲:24ns @ 6V，50pF 觸發(fā)器類型:正邊沿 電流 - 輸出高，低:5.2mA，5.2mA 電壓 - 電源:2 V ~ 6 V 電流 - 靜態(tài):4μA 輸入電容:3pF 工作溫度:-40°C ~ 125°C（TA） 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 標(biāo)準(zhǔn)包裝:1 |
| 74HC175D,652 | 功能描述:觸發(fā)器 QUAD D F/F POS-EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HC175D,653 | 功能描述:觸發(fā)器 QUAD D-TYPE MASTER RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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